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Multiphase PWM Regulator for IMVP-6.5TM Mobile CPUs and GPUs
ISL62882, ISL62882B
The ISL62882 is a multiphase PWM buck regulator for miroprocessor or graphics processor core power supply. The multiphase buck converter uses interleaved phases to reduce the total output voltage ripple with each phase carrying a portion of the total load current, providing better system performance, superior thermal management, lower component cost, reduced power dissipation, and smaller implementation area. The ISL62882 uses two integrated gate drivers to provide a complete solution. The PWM modulator is based on Intersil's Robust Ripple Regulator (R3) technologyTM. Compared with traditional modulators, the R3TM modulator commands variable switching frequency during load transients, achieving faster transient response. With the same modulator, the switching frequency is reduced at light load, increasing the regulator efficiency. The ISL62882 can be configured as CPU or graphics Vcore controller and is fully compliant with IMVP-6.5TM specifications. It responds to PSI# and DPRSLPVR signals by adding or dropping Phase 2, adjusting overcurrent protection threshold accordingly, and entering/exiting diode emulation mode. It reports the regulator output current through the IMON pin. It senses the current by using either discrete resistor or inductor DCR whose variation over temperature can be thermally compensated by a single NTC thermistor. It uses differential remote voltage sensing to accurately regulate the processor die voltage. The unique split LGATE function further increases light load efficiency. The adaptive body diode conduction time reduction function minimizes the body diode conduction loss in diode emulation mode. User-selectable overshoot reduction function offers an option to aggressively reduce the output capacitors as well as the option to disable it for users concerned about increased system thermal stress. The ISL62882 offers the FB2 function to optimize 1-phase performance. The ISL62882B has the same functions as the ISL62882, but comes in a different package.
ISL62882, ISL62882B
Features
* Programmable 1- or 2-Phase CPU Mode Operation or 1-Phase GPU Mode Operation * Precision Multiphase Core Voltage Regulation - 0.5% System Accuracy Over-Temperature - Enhanced Load Line Accuracy * Microprocessor Voltage Identification Input - 7-Bit VID Input, 0V to 1.500V in 12.5mV Steps - Supports VID Changes On-The-Fly * Supports Multiple Current Sensing Methods - Lossless Inductor DCR Current Sensing - Precision Resistor Current Sensing * Supports PSI# and DPRSLPVR modes * Superior Noise Immunity and Transient Response * Current Monitor and Thermal Monitor * Differential Remote Voltage Sensing * High Efficiency Across Entire Load Range * Programmable 1- or 2-Phase Operation * Two Integrated Gate Drivers * Excellent Dynamic Current Balance Between Phases * Split LGATE1 Drivers Increases Light Load Efficiency * FB2 Function Optimizes 1-Phase Mode Performance * Adaptive Body Diode Conduction Time Reduction * User-selectable Overshoot Reduction Function * Small Footprint 40 Ld 5x5 or 48 Ld 6x6 TQFN Packages * Pb-Free (RoHS Compliant)
Applications
* Notebook Core Voltage Regulator * Notebook GPU Voltage Regulator
April 29, 2010 FN6890.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2009, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL62882, ISL62882B
Ordering Information
PART NUMBER (Note 3) ISL62882IRTZ (Note 2) ISL62882IRTZ-T (Notes 1, 2) ISL62882HRTZ (Note 2) ISL62882HRTZ-T (Notes 1, 2) ISL62882BHRTZ (Note 2) ISL62882BHRTZ-T (Notes 1, 2) NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL62882, ISL62882B. For more information on MSL please see techbrief TB363. PART MARKING 62882 IRTZ 62882 IRTZ 62882 HRTZ 62882 HRTZ 62882 BHRTZ 62882 BHRTZ TEMP. RANGE (C) -40 to +100 -40 to +100 -10 to +100 -10 to +100 -10 to +100 -10 to +100 PACKAGE (Pb-Free) 40 Ld 5x5 TQFN 40 Ld 5x5 TQFN 40 Ld 5x5 TQFN 40 Ld 5x5 TQFN 48 Ld 6x6 TQFN 48 Ld 6x6 TQFN PKG. DWG. # L40.5x5 L40.5x5 L40.5x5 L40.5x5 L48.6x6 L48.6x6
Pin Configurations
ISL62882 (40 LD TQFN) TOP VIEW
DPRSLPVR CLK_EN#
ISL62882B (48 LD TQFN) TOP VIEW
DPRSLPVR CLK_EN# VR_ON
VR_ON
VID5
VID6
VID3
VID2
VID4
VID1
VID6
VID4
VID3
VID2
VID1
VID0
VID5
VID0
40 39 38 37 36 35 34 33 32 31 PGOOD 1 PSI# 2 RBIAS 3 VR_TT# 4 NTC 5 VW 6 GND PAD (BOTTOM) 30 BOOT2 29 UGATE2 28 PHASE2 27 VSSP2 26 LGATE2 25 VCCP 24 LGATE1b 23 LGATE1a 22 VSSP1 21 PHASE1 11 12 13 14 15 16 17 18 19 20 ISUM+ BOOT1 UGATE1 ISEN1 VDD IMON VSEN RTN ISUMVIN NC 1 PGOOD 2 PSI# 3 RBIAS 4 VR_TT# 5 NTC 6 GND 7 VW 8 COMP 9 FB 10 FB2 11 NC 12
NC
48 47 46 45 44 43 42 41 40 39 38 37 36 BOOT2 35 UGATE2 34 PHASE2 33 VSSP2 32 LGATE2 (BOTTOM) 31 NC 30 VCCP 29 LGATE1b 28 LGATE1a 27 VSSP1 26 PHASE1 25 UGATE1 13 14 15 16 17 18 19 20 21 22 23 24 ISUM+ BOOT1
FN6890.2 April 29, 2010
COMP 7 FB 8 FB2 9 ISEN2 10
ISEN2
ISEN1
VDD
RTN
IMON
VSEN
NC
ISUM-
2
VIN
NC
NC
ISL62882, ISL62882B
Functional Pin Descriptions
ISL62882 ISL62882B 1 7 2 SYMBOL GND PGOOD DESCRIPTION Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin. Power-Good open-drain output indicating when the regulator is able to supply regulated voltage. Pull-up externally with a 680 resistor to VCCP or 1.9k to 3.3V. Low load current indicator input. When asserted low, indicates a reduced load current condition. A resistor to GND sets internal current reference. Use 147k or 47k. The choice of Rbias value, together with the ISEN2 pin configuration and the external resistance from the COMP pin to GND, programs the controller to enable/disable the overshoot reduction function and to select the CPU/GPU mode. Thermal overload output indicator. Thermistor input to VR_TT# circuit. A resistor from this pin to COMP programs the switching frequency (8k gives approximately 300kHz). This pin is the output of the error amplifier. Also, a resistor across this pin and GND adjusts the overcurrent threshold. This pin is the inverting input of the error amplifier. There is a switch between the FB2 pin and the FB pin. The switch is on in 2-phase mode and is off in 1-phase mode. The components connecting to FB2 are used to adjust the compensation in 1-phase mode to achieve optimum performance. Individual current sensing for Phase 2. When ISEN2 is pulled to 5V VDD, the controller will disable Phase 2. Individual current sensing for phase 1. Remote core voltage sense input. Connect to microprocessor die. Remote voltage sensing return. Connect to ground at microprocessor die.
2 3
3 4
PSI# RBIAS
4 5 6 7 8 9
5 6 8 9 10 11
VR_TT# NTC VW COMP FB FB2
10 11 12 13 14, 15 16 17 18 19
13 14 15 16 17, 18 19 20 22 24
ISEN2 ISEN1 VSEN RTN
ISUM- and ISUM+ Droop current sense input. VDD VIN IMON BOOT1 5V bias power. Battery supply voltage, used for feed-forward. An analog output. IMON outputs a current proportional to the regulator output current. Connect an MLCC capacitor across the BOOT1 and the PHASE1 pins. The boot capacitor is charged through an internal boot diode connected from the VCCP pin to the BOOT1 pin, each time the PHASE1 pin drops below VCCP minus the voltage dropped across the internal boot diode. Output of the Phase-1 high-side MOSFET gate driver. Connect the UGATE1 pin to the gate of the Phase-1 high-side MOSFET. Current return path for the Phase-1 high-side MOSFET gate driver. Connect the PHASE1 pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase-1. Current return path for the Phase-1 low-side MOSFET gate driver. Connect the VSSP1 pin to the source of the Phase-1 low-side MOSFET through a low impedance path, preferably in parallel with the traces connecting the LGATE1a and the LGATE1b pins to the gates of the Phase-1 low-side MOSFETs. Output of the Phase-1 low-side MOSFET gate driver that is always active. Connect the LGATE1a pin to the gate of the Phase-1 low-side MOSFET that is active all the time.
20 21
25 26
UGATE1 PHASE1
22
27
VSSP1
23
28
LGATE1a
3
FN6890.2 April 29, 2010
ISL62882, ISL62882B
Functional Pin Descriptions (Continued)
ISL62882 ISL62882B 24 29 SYMBOL LGATE1b DESCRIPTION Another output of the Phase-1 low-side MOSFET gate driver. This gate driver will be pulled low when the DPRSLPVR pin logic is high. Connect the LGATE1b pin to the gate of the Phase-1 low-side MOSFET that is idle in deeper sleep mode. Output of the Phase-1 low-side MOSFET gate driver. Connect the LGATE1 pin to the gate of the Phase-1 low-side MOSFET. Input voltage bias for the internal gate drivers. Connect +5V to the VCCP pin. Decouple with at least 1F of an MLCC capacitor to VSSP1 and VSSP2 pins respectively. Output of the Phase-2 low-side MOSFET gate driver. Connect the LGATE2 pin to the gate of the Phase-2 low-side MOSFET. Current return path for the Phase-2 converter low-side MOSFET gate driver. Connect the VSSP2 pin to the source of the Phase-2 low-side MOSFET through a low impedance path, preferably in parallel with the trace connecting the LGATE2 pin to the gate of the Phase-2 low-side MOSFET. Current return path for the Phase-2 high-side MOSFET gate driver. Connect the PHASE2 pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase-2. Output of the Phase-2 high-side MOSFET gate driver. Connect the UGATE2 pin to the gate of the Phase-2 high-side MOSFET. Connect an MLCC capacitor across the BOOT2 and the PHASE2 pins. The boot capacitor is charged through an internal boot diode connected from the VCCP pin to the BOOT2 pin, each time the PHASE2 pin drops below VCCP minus the voltage dropped across the internal boot diode. VID input with VID0 = LSB and VID6 = MSB. Voltage regulator enable input. A high level logic signal on this pin enables the regulator. Deeper sleep enable signal. A high level logic signal on this pin indicates that the microprocessor is in deeper sleep mode. Open drain output to enable system PLL clock. It goes low 13 switching cycles after Vcore is within 10% of Vboot. No connect. The bottom pad of ISL62882B is electrically connected to the GND pin inside the IC.
25
30
LGATE1 VCCP
26 27
32 33
LGATE2 VSSP2
28
34
PHASE2
29 30
35 36
UGATE2 BOOT2
31 thru 37 38 39 40 pad
38 thru 44 45 46 47 48 pad
VID0 thru VID6 VR_ON DPRSLPVR CLK_EN# NC BOTTOM
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FN6890.2 April 29, 2010
ISL62882, ISL62882B
Block Diagram
VIN VSEN ISEN2 ISEN1 PGOOD CLK_EN# VDD
VR_ON PSI# DPRSLPVR IBAL RBIAS PROTECTION VID0 VID1 VIN VID2 VID3 VID4 VID5 VID6 DAC AND SOFTSTART MODULATOR CLOCK VDAC COMP VW COMP IBAL WOC OC VIN VDAC FLT MODE CONTROL PGOOD & CLK_EN# LOGIC
6A
54A 1.20V 1.24V
VR_TT#
CURRENT BALANCE
NTC BOOT2 DRIVER PWM CONTROL LOGIC UGATE2 PHASE2 SHOOT THROUGH PROTECTION
DRIVER
LGATE2
VSSP2 BOOT1
E/A
PWM CONTROL LOGIC
RTN FB COMP VW
DRIVER
UGATE1 PHASE1
IBAL
VIN VDAC
SHOOT THROUGH PROTECTION VCCP DRIVER LGATE1A VSSP1
MODULATOR IDROOP
FB2 IMON IMON ISUM+ ISUM2.5X CURRENT SENSE
WOC CURRENT COMPARATORS OC NUMBER OF PHASES
COMP 60A DRIVER LGATE1B
GAIN SELECT
ADJ. OCP THRESHOLD
COMP
GND
5
FN6890.2 April 29, 2010
ISL62882, ISL62882B
Absolute Maximum Ratings
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . .-0.3V to +7V Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . +28V Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . -0.3V to +33V Boot to Phase Voltage (BOOT-PHASE) . . . . -0.3V to +7V(DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V(<10ns) Phase Voltage (PHASE) . . . . . -7V (<20ns Pulse Width, 10J) UGATE Voltage (UGATE) . . . . . . . PHASE-0.3V (DC) to BOOT . . . . . . . . . PHASE-5V (<20ns Pulse Width, 10J) to BOOT LGATE1a and 1b and LGATE2 Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V (DC) to VDD+0.3V LGATE1a and 1b . . . . . . . . . -2.5V (<20ns Pulse Width, 2.5J) to VDD+0.3V LGATE1a and 1b . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5J) to VDD+0.3V All Other Pins. . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V) Open Drain Outputs, PGOOD, VR_TT#, CLK_EN# . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 40 Ld TQFN Package (Notes 4, 5). . 32 3 48 Ld TQFN Package (Notes 4, 5). . 29 2 Maximum Junction Temperature . . . . . . . . . . . . . . . +150C Maximum Storage Temperature Range . . . -65C to +150C Maximum Junction Temperature (Plastic Package). . . +150C Storage Temperature Range . . . . . . . . . . . -65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . Battery Voltage, VIN . . . . . . . . . . Ambient Temperature ISL62882HRTZ, ISL62882BHRTZ ISL62882IRTZ . . . . . . . . . . . . . Junction Temperature ISL62882HRTZ, ISL62882BHRTZ ISL62882IRTZ . . . . . . . . . . . . . . . . . . . . . . . . +5V 5% . . . . . . . . . +4.5V to 25V . . . . . . -10C to +100C . . . . . . -40C to +100C . . . . . . -10C to +125C . . . . . . -40C to +125C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -40C to +100C, fSW = 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +100C. SYMBOL IVDD IVIN RVIN PORr PORf TEST CONDITIONS VR_ON = 3.3V VR_ON = 0V VR_ON = 0V VR_ON = 3.3V VDD rising VDD falling No load; closed loop, active mode range VID = 0.75V to 1.50V, VID = 0.5V to 0.7375V VID = 0.3V to 0.4875V IRTZ %Error (VCC_CORE) No load; closed loop, active mode range VID = 0.75V to 1.50V VID = 0.5V to 0.7375V VID = 0.3V to 0.4875V 4.00 900 4.35 4.15 4.5 MIN (Note 6) TYP 4 MAX (Note 6) 4.6 1 1 UNITS mA A A k V V
PARAMETER INPUT POWER SUPPLY +5V Supply Current Battery Supply Current VIN Input Resistance Power-On-Reset Threshold SYSTEM AND REFERENCES System Accuracy
HRTZ %Error (VCC_CORE)
-0.5 -8 -15
+0.5 +8 +15
% mV mV
-0.8 -10 -18 1.0945 1.100 1.500 0.300 1.45 1.47
+0.8 +10 +18 1.1055
% mV mV V V V
VBOOT Maximum Output Voltage Minimum Output Voltage RBIAS Voltage VCC_CORE(max) VID = [0000000] VCC_CORE(min) VID = [1100000] RBIAS = 147k
1.49
V
6
FN6890.2 April 29, 2010
ISL62882, ISL62882B
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -40C to +100C, fSW = 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +100C. (Continued) SYMBOL fSW(nom) TEST CONDITIONS Rfset = 7k, 2-channel operation, VCOMP = 1V MIN (Note 6) 285 200 IFB = 0A Av0 GBW CL = 20pF -0.15 90 18 TYP 300 MAX (Note 6) 315 500 +0.15 UNITS kHz kHz mV dB MHz
PARAMETER CHANNEL FREQUENCY Nominal Channel Frequency Adjustment Range AMPLIFIERS Current-Sense Amplifier Input Offset Error Amp DC Gain (Note 7) Error Amp Gain-Bandwidth Product (Note 7) ISEN Imbalance Voltage Input Bias Current
Maximum of ISENs - Minimum of ISENs 20 VOL IOH tpgd RUGPU IUGSRC RUGPD IUGSNK RLGPU ILGSRC RLGPD ILGSNK tUGFLGR tLGFUGR RLGPU ILGSRC RLGPD ILGSNK tUGFLGR tLGFUGR VF IR OVH IPGOOD = 4mA PGOOD = 3.3V CLK_ENABLE# LOW to PGOOD HIGH 200mA Source Current UGATE - PHASE = 2.5V 250mA Sink Current UGATE - PHASE = 2.5V 250mA Source Current LGATE1a and 1b - VSSP1 = 2.5V 250mA Sink Current LGATE1a and 1b - VSSP1 = 2.5V UGATE1 falling to LGATE1a and 1b rising, no load LGATE1a and 1b falling to UGATE1 rising, no load 250mA Source Current LGATE - VSSP = 2.5V 250mA Sink Current LGATE - VSSP = 2.5V UGATE falling to LGATE rising, no load LGATE falling to UGATE rising, no load PVCC = 5V, IF = 2mA VR = 25V VSEN rising above setpoint for >1ms 150 -1 6.3 7.6 1.0 2.0 1.0 2.0 2.0 1.0 1 2.0 23 28 1.0 2.0 0.5 4.0 23 28 0.58 0.2 195 0.26
1
mV nA
POWER-GOOD AND PROTECTION MONITORS PGOOD Low Voltage PGOOD Leakage Current PGOOD Delay GATE DRIVER UGATE Pull-Up Resistance (Note 7) UGATE Source Current (Note 7) UGATE Sink Resistance (Note 7) UGATE Sink Current (Note 7) LGATE1a and 1b Pull-Up Resistance (Note 7) LGATE1a and 1b Source Current (Note 7) LGATE1a and 1b Sink Resistance (Note 7) LGATE1a and 1b Sink Current (Note 7) UGATE1 to LGATE1a and 1b Deadtime LGATE1a and 1b to UGATE1 Deadtime LGATE Pull-Up Resistance (Note 7) LGATE Source Current (Note 7) LGATE Sink Resistance (Note 7) LGATE Sink Current (Note 7) UGATE to LGATE Deadtime LGATE to UGATE Deadtime BOOTSTRAP DIODE Forward Voltage Reverse Leakage PROTECTION Overvoltage Threshold 240 mV V A 1.5 1.5 3 A A A 1.8 A ns ns 1.5 0.9 A A ns ns 0.4 1 8.9 V A ms
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FN6890.2 April 29, 2010
ISL62882, ISL62882B
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -40C to +100C, fSW = 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +100C. (Continued) SYMBOL OVHS TEST CONDITIONS VSEN rising for >2s 2-phase configuration, ISUM- pin current 1-phase configuration, ISUM- pin current Current Imbalance Threshold Undervoltage Threshold LOGIC THRESHOLDS VR_ON Input Low VR_ON Input High VID0-VID6, PSI#, and DPRSLPVR Input Low VID0-VID6, PSI#, and DPRSLPVR Input High THERMAL MONITOR NTC Source Current Over-Temperature Threshold VR_TT# Low Output Resistance CLK_EN# OUTPUT LEVELS CLK_EN# Low Output Voltage CLK_EN# Leakage Current CURRENT MONITOR IMON Output Current IIMON ISUM- pin current = 20A ISUM- pin current = 10A ISUM- pin current = 5A IMON Clamp Voltage Current Sinking Capability INPUTS VR_ON Leakage Current VIDx Leakage Current PSI# Leakage Current DPRSLPVR Leakage Current SLEW RATE Slew Rate (For VID Change) NOTES: 6. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 7. Limits established by characterization and are not production tested. SR 5 6.5 mV/s IVR_ON IVIDx IPSI# IDPRSLPVR VR_ON = 0V VR_ON = 1V VIDx = 0V VIDx = 1V PSI# = 0V PSI# = 1V DPRSLPVR = 0V DPRSLPVR = 1V -1 -1 -1 -1 0 0 0 0.45 0 0.45 0 0.45 1 1 1 1 A A A A A A A A VIMONCLAMP 108 51 22 120 60 30 1.1 275 132 69 37.5 1.15 A A A V A VOL IOH I = 4mA CLK_EN# = 3.3V -1 0.26 0.4 1 V A RTT NTC = 1.3V V (NTC) falling I = 20mA 53 1.18 60 1.2 6.5 67 1.22 9 A V VIL(1.0V) VIH(1.0V) VIH(1.0V) VIL(1.0V) VIH(1.0V) 0.7 ISL62882HRTZ ISL62882IRTZ 0.7 0.75 0.3 0.3 V V V V V UVf One ISEN above another ISEN for >1.2ms VSEN falling below setpoint for >1.2ms -355 MIN (Note 6) 1.525 18.3 8.2 TYP 1.55 20.2 10.1 9 -295 -235 MAX (Note 6) 1.575 22.1 12.0 UNITS V A A mV mV
PARAMETER Severe Overvoltage Threshold OC Threshold Offset at Rcomp = Open Circuit
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FN6890.2 April 29, 2010
ISL62882, ISL62882B
Gate Driver Timing Diagram
PWM
tLGFUGR
tRU 1V
tFU
UGATE
LGATE tFL
1V tRL
tUGFLGR
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FN6890.2 April 29, 2010
ISL62882, ISL62882B
Simplified Application Circuits
V+5 Rbias Rntc
o
V+5
Vin
VDD VCCP VIN RBIAS
C
NTC PGOOD VR_TT# CLK_EN# VIDs PSI# DPRSLPVR VR_ON VW Rfset
BOOT2 UGATE2 PHASE2 LGATE2 VSSP2 ISEN2 Cs2 BOOT1
Vin L2 Vo
PGOOD VR_TT# CLK_EN# VID<0:6> PSI# DPRSLPVR VR_ON
Rs2
ISL62882
Rdroop
COMP FB2 FB VSEN
UGATE1 PHASE1 LGATE1b LGATE1a VSSP1 ISEN1 Cs1 ISUM+
L1
Rs1
Rsum2 VCCSENSE VSSSENSE Rimon IMON IMON (Bottom Pad) VSS ISUMRis RTN Cis Ri Cn
o
Rn C
Rsum1
FIGURE 1. TYPICAL CPU APPLICATION CIRCUIT USING DCR SENSING
V+5 Rbias Rntc
o
V+5
Vin
VDD VCCP VIN RBIAS
C
NTC PGOOD VR_TT# CLK_EN# VIDs PSI# DPRSLPVR VR_ON VW Rfset
BOOT2 UGATE2 PHASE2 LGATE2 VSSP2 ISEN2 Cs2 BOOT1
Vin L2 Rsen2 Vo
IMVP6_PWRGD VR_TT# CLK_ENABLE VID<0:6> # PSI# DPRSLPVR VR_ON
Rs2
ISL62882
Rdroop
COMP FB2 FB VSEN
UGATE1 PHASE1 LGATE1b LGATE1a VSSP1 ISEN1 Cs1 ISUM+
L1
Rsen1
Rs1
Rsum2 VCCSENSE VSSSENSE Rimon IMON IMON (Bottom Pad) VSS ISUMRis RTN Cis Ri Cn Rsum1
FIGURE 2. TYPICAL CPU APPLICATION CIRCUIT USING RESISTOR SENSING
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FN6890.2 April 29, 2010
ISL62882, ISL62882B
V+5 Rbias Rntc
o
V+5
Vin
VDD VCCP VIN RBIAS
C
NTC PGOOD VR_TT# CLK_EN# VIDs PSI# DPRSLPVR VR_ON VW Rfset
BOOT2 UGATE2 PHASE2 LGATE2 VSSP2 ISEN2
PGOOD VR_TT# CLK_EN# VID<0:6> PSI# DPRSLPVR VR_ON
ISL62882
BOOT1
Vin L Vo
COMP FB2 FB VSEN
UGATE1 PHASE1 LGATE1b LGATE1a VSSP1 ISEN1
Rdroop
ISUM+ Rsum VCCSENSE VSSSENSE Rimon IMON IMON (Bottom Pad) VSS ISUMRis RTN Cis Ri Cn
o
Rn C
FIGURE 3. TYPICAL GPU APPLICATION CIRCUIT USING DCR SENSING
V+5 Rbias Rntc
o
V+5
Vin
VDD VCCP VIN RBIAS
C
NTC PGOOD VR_TT# CLK_EN# VIDs PSI# DPRSLPVR VR_ON VW Rfset
BOOT2 UGATE2 PHASE2 LGATE2 VSSP2 ISEN2
IMVP6_PWRGD VR_TT# CLK_ENABLE VID<0:6> # PSI# DPRSLPVR VR_ON
ISL62882
BOOT1
Vin L Rsen Vo
COMP FB2 FB VSEN
UGATE1 PHASE1 LGATE1b LGATE1a VSSP1 ISEN1
Rdroop
ISUM+ Rsum2 VCCSENSE VSSSENSE Rimon IMON IMON (Bottom Pad) VSS ISUMRis RTN Cis Ri Cn
FIGURE 4. TYPICAL GPU APPLICATION CIRCUIT USING RESISTOR SENSING
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FN6890.2 April 29, 2010
ISL62882, ISL62882B
Theory of Operation
Multiphase R3TM Modulator
Master Clock Circuit Master Clock Master COMP Phase Clock Vcrm Sequencer VW gmVo Crm Slave Circuit 1 Clock1 S PWM1 Phase1 Q R L1 IL1 Vcrs1 Crs1 Slave Circuit 2 Phase2 S PWM2 Q R gm Vo
Clock2
VW
COMP Vcrm
Clock1 Clock2
Master Clock Clock1
VW VW
PWM1
Co
PWM2 VW
VW
Clock2
L2 IL2
Vcrs1 Vcrs2
Vcrs2 Crs2
gm
FIGURE 7. R3TM MODULATOR OPERATION PRINCIPLES IN LOAD INSERTION RESPONSE
FIGURE 5. R3TM MODULATOR CIRCUIT
VW Vcrm COMP Master Clock Clock1 PWM1 Clock2 PWM2 VW Hysteretic Window
The ISL62882 is a multiphase regulator implementing Intel(R) IMVP-6.5TM protocol. It can be programmed for 1- or 2-phase operation for microprocessor core applications. It uses Intersil patented R3TM (Robust Ripple RegulatorTM) modulator. The R3TM modulator combines the best features of fixed frequency PWM and hysteretic PWM while eliminating many of their shortcomings. Figure 5 conceptually shows the ISL62882 multiphase R3TM modulator circuit, and Figure 6 shows the operation principles. A current source flows from the VW pin to the COMP pin, creating a voltage window set by the resistor between the two pins. This voltage window is called VW window in the following discussion. Inside the IC, the modulator uses the master clock circuit to generate the clocks for the slave circuits. The modulator discharges the ripple capacitor Crm with a current source equal to gmVo, where gm is a gain factor. Crm voltage Vcrm is a sawtooth waveform traversing between the VW and COMP voltages. It resets to VW when it hits COMP, and generates a one-shot master clock signal. A phase sequencer distributes the master clock signal to the slave circuits. If the ISL62882 is in 2phase mode, the master clock signal will be distributed to Phases 1 and 2, and the Clock1 and Clock2 signals will be 180 out-of-phase. If the ISL62882 is in 1-phase mode, the master clock signal will be distributed to Phases 1 only and be the Clock1 signal. Each slave circuit has its own ripple capacitor Crs, whose voltage mimics the inductor ripple current. A gm amplifier converts the inductor voltage into a current source to charge and discharge Crs. The slave circuit turns on its PWM pulse upon receiving the clock signal, and the current source charges Crs. When Crs voltage
Vcrs2
Vcrs1
FIGURE 6. R3TM MODULATOR OPERATION PRINCIPLES IN STEADY STATE
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VCrs hits VW, the slave circuit turns off the PWM pulse, and the current source discharges Crs. Since the ISL62882 works with Vcrs, which are large amplitude and noise-free synthesized signals, the ISL62882 achieves lower phase jitter than conventional hysteretic mode and fixed PWM mode controllers. Unlike conventional hysteretic mode converters, the ISL62882 has an error amplifier that allows the controller to maintain a 0.5% output voltage accuracy. Figure 7 shows the operation principles during load insertion response. The COMP voltage rises during load insertion, generating the master clock signal more quickly, so the PWM pulses turn on earlier, increasing the effective switching frequency, which allows for higher control loop bandwidth than conventional fixed frequency PWM controllers. The VW voltage rises as the COMP voltage rises, making the PWM pulses wider. During load release response, the COMP voltage falls. It takes the master clock circuit longer to generate the next master clock signal so the PWM pulse is held off until needed. The VW voltage falls as the VW voltage falls, reducing the current PWM pulse width. This kind of behavior gives the ISL62882 excellent response speed. The fact that both phases share the same VW window voltage also ensures excellent dynamic current balance between phases. current is heavy enough, the inductor current will never reach 0A, and the regulator is in CCM although the controller is in DE mode. Figure 9 shows the operation principle in diode emulation mode at light load. The load gets incrementally lighter in the three cases from top to bottom. The PWM on-time is determined by the VW window size, therefore is the same, making the inductor current triangle the same in the three cases. The ISL62882 clamps the ripple capacitor voltage Vcrs in DE mode to make it mimic the inductor current. It takes the COMP voltage longer to hit Vcrs, naturally stretching the switching period. The inductor current triangles move further apart from each other such that the inductor current average value is equal to the load current. The reduced switching frequency helps to increase light load efficiency.
CCM/DCM BOUNDARY VW Vcrs
iL LIGHT DCM
VW Vcrs
Diode Emulation and Period Stretching
iL
PHASE
DEEP DCM VW Vcrs
UGATE
LGATE
iL
IL
FIGURE 9. PERIOD STRETCHING
Start-up Timing
FIGURE 8. DIODE EMULATION
ISL62882 can operate in diode emulation (DE) mode to improve light load efficiency. In DE mode, the low-side MOSFET conducts when the current is flowing from source to drain and does not allow reverse current, emulating a diode. As Figure 8 shows, when LGATE is on, the low-side MOSFET carries current, creating negative voltage on the phase node due to the voltage drop across the ON-resistance. The ISL62882 monitors the current through monitoring the phase node voltage. It turns off LGATE when the phase node voltage reaches zero to prevent the inductor current from reversing the direction and creating unnecessary power loss. If the load current is light enough, as Figure 8 shows, the inductor current will reach and stay at zero before the next phase node pulse, and the regulator is in discontinuous conduction mode (DCM). If the load 13
With the controller's VDD voltage above the POR threshold, the start-up sequence begins when VR_ON exceeds the 3.3V logic high threshold. Figure 10 shows the typical start-up timing when the ISL62882 is configured for CPU VR application. The ISL62882 uses digital soft-start to ramp-up DAC to the boot voltage of 1.1V at about 2.5mV/s. Once the output voltage is within 10% of the boot voltage for 13 PWM cycles (43s for frequency = 300kHz), CLK_EN# is pulled low and DAC slews at 5mV/s to the voltage set by the VID pins. PGOOD is asserted high in approximately 7ms. Similar results occur if VR_ON is tied to VDD, with the soft-start sequence starting 120s after VDD crosses the POR threshold. Figure 11 shows the typical start-up timing when the ISL62882 is configured for GPU VR application. The ISL62882 uses digital soft start to ramp up DAC to the
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TABLE 1. VID TABLE (Continued)
VDD VR_ON 5mV/s 2.5mV/s 90% Vboot 800s DAC 13 SWITCHING CYCLES CLK_EN# ~7ms PGOOD VID COMMAND VOLTAGE
VID6 0 0 0 0 0 0 0 0 0 0 0
VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VID4 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
VID3 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
VID2 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
VO (V) 1.4250 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 1.2250 1.2125 1.2000 1.1875 1.1750 1.1625 1.1500 1.1375 1.1250 1.1125 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000
FIGURE 10. SOFT-START WAVEFORMS FOR CPU VR APPLICATION
VDD VR_ON SLEW RATE 90% 120s
0
VID COMMAND VOLTAGE
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VO (V) 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 0 0 0 0 0 0 0 0
DAC 13 SWITCHING CYCLES CLK_EN# ~7ms PGOOD
FIGURE 11. SOFT-START WAVEFORMS FOR GPU VR APPLICATION
voltage set by the VID pins. The slew rate is 5mV/s when there is DPRSLPVR = 0, and is doubled when there is DPRSLPVR = 1. Once the output voltage is within 10% of the target voltage for 13 PWM cycles (43s for frequency = 300kHz), CLK_EN# is pulled low. PGOOD is asserted high in approximately 7ms. Similar results occur if VR_ON is tied to VDD, with the soft-start sequence starting 120s after VDD crosses the POR threshold.
Voltage Regulation and Load Line Implementation
After the start sequence, the ISL62882 regulates the output voltage to the value set by the VID inputs per Table 1. The ISL62882 will control the no-load output voltage to an accuracy of 0.5% over the range of 0.75V to 1.5V. A differential amplifier allows voltage sensing for precise voltage regulation at the microprocessor die.
TABLE 1. VID TABLE VID6 0 0 0 0 0 0 VID5 0 0 0 0 0 0 VID4 0 0 0 0 0 0 VID3 0 0 0 0 0 0 VID2 0 0 0 0 1 1 VID1 0 0 1 1 0 0 VID0 0 1 0 1 0 1
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TABLE 1. VID TABLE (Continued) VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 VID2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VO (V) 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 0.3625 VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TABLE 1. VID TABLE (Continued) VID5 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VO (V) 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875 0.2750 0.2625 0.2500 0.2375 0.2250 0.2125 0.2000 0.1875 0.1750 0.1625 0.1500 0.1375 0.1250 0.1125 0.1000 0.0875 0.0750 0.0625 0.0500 0.0375 0.0250 0.0125 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000 0.0000
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Rewriting Equation 3 and substitution of Equation 2 gives
Rdroop Vdroop FB Idroop E/A COMP VR LOCAL "CATCH" VO RESISTOR VIDs VID<0:6> RTN VSSSENSE VCCSENSE
VCCSENSE - VSS SENSE = V DAC - R droop x I droop
(EQ. 4)
Equation 4 is the exact equation required for load line implementation. The VCCSENSE and VSSSENSE signals come from the processor die. The feedback will be open circuit in the absence of the processor. As Figure 12 shows, it is recommended to add a "catch" resistor to feed the VR local output voltage back to the compensator, and add another "catch" resistor to connect the VR local output ground to the RTN pin. These resistors, typically 10~100, will provide voltage feedback if the system is powered up without a processor installed.
VDAC DAC
X1
INTERNAL TO IC
VSS "CATCH" RESISTOR
FIGURE 12. DIFFERENTIAL SENSING AND LOAD LINE IMPLEMENTATION
Phase Current Balancing
L2 PHASE2 ISEN2 CS INTERNAL TO IC PHASE1 RS CS IL1 RS IL2 L1 RDCR1 RPCB1 VO RDCR2 RPCB2
As the load current increases from zero, the output voltage will droop from the VID table value by an amount proportional to the load current to achieve the load line. The ISL62882 can sense the inductor current through the intrinsic DC Resistance (DCR) of the inductors as shown in Figure 1 or through resistors in series with the inductors as shown in Figure 2. In both methods, capacitor Cn voltage represents the inductor total currents. A droop amplifier converts Cn voltage into an internal current source with the gain set by resistor Ri. The current source is used for load line implementation, current monitor and overcurrent protection. Figure 12 shows the load line implementation. The ISL62882 drives a current source Idroop out of the FB pin, described by Equation 1.
2xV Cn I droop = ----------------Ri (EQ. 1)
ISEN1
FIGURE 13. CURRENT BALANCING CIRCUIT
When using inductor DCR current sensing, a single NTC element is used to compensate the positive temperature coefficient of the copper winding thus sustaining the load line accuracy with reduced cost. Idroop flows through resistor Rdroop and creates a voltage drop as shown in Equation 2.
V droop = R droop x I droop (EQ. 2)
The ISL62882 monitors individual phase average current by monitoring the ISEN1 and ISEN2 voltages. Figure 13 shows the current balancing circuit recommended for ISL62882. Each phase node voltage is averaged by a low-pass filter consisting of Rs and Cs, and presented to the corresponding ISEN pin. Rs should be routed to inductor phase-node pad in order to eliminate the effect of phase node parasitic PCB DCR. Equations 5 and 6 give the ISEN pin voltages:
V ISEN1 = ( R dcr1 + R pcb1 ) x I L1 V ISEN2 = ( R dcr2 + R pcb2 ) x I L2 (EQ. 5) (EQ. 6)
where Rdcr1 and Rdcr2 are inductor DCR; Rpcb1 and Rpcb2 are parasitic PCB DCR between the inductor output side pad and the output voltage rail; and IL1 and IL2 are inductor average currents. The ISL62882 will adjust the phase pulse-width relative to the other phase to make VISEN1 = VISEN2, thus to achieve IL1 = IL2, when there are Rdcr1 = Rdcr2 and Rpcb1 = Rpcb2. Using same components for L1 and L2 will provide a good match of Rdcr1 and Rdcr2. Board layout will determine Rpcb1 and Rpcb2. It is recommended to have symmetrical layout for the power delivery path between each inductor and the output voltage rail, such that Rpcb1 = Rpcb2.
Vdroop is the droop voltage required to implement load line. Changing Rdroop or scaling Idroop can both change the load line slope. Since Idroop also sets the overcurrent protection level, it is recommended to first scale Idroop based on OCP requirement, then select an appropriate Rdroop value to obtain the desired load line slope.
Differential Sensing
Figure 12 also shows the differential voltage sensing scheme. VCCSENSE and VSSSENSE are the remote voltage sensing signals from the processor die. A unity gain differential amplifier senses the VSSSENSE voltage and add it to the DAC output. The error amplifier regulates the inverting and the non-inverting input voltages to be equal as shown in Equation 3:
VCC SENSE + V
droop
= V DAC + VSS SENSE
(EQ. 3)
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L2 Rdcr2 V2n Rpcb2
ISEN2
PHASE2 Rs Cs Rs Rs Rs Cs
V2p
REP RATE = 10kHz
IL2 VO
INTERNAL TO IC
ISEN1
L1 PHASE1 V1p IL1
Rdcr1 V1n
Rpcb1
FIGURE 14. DIFFERENTIAL-SENSING CURRENT BALANCING CIRCUIT
REP RATE = 25kHz
Sometimes, it is difficult to implement symmetrical layout. For the circuit Figure 13 shows, asymmetric layout causes different Rpcb1 and Rpcb2 thus current imbalance. Figure 14 shows a differential-sensing current balancing circuit recommended for ISL62882. The current sensing traces should be routed to the inductor pads so they only pick up the inductor DCR voltage. Each ISEN pin sees the average voltage of two sources: its own phase inductor phase-node pad, and the other phase inductor output side pad. Equations 7 and 8 give the ISEN pin voltages:
V ISEN1 = V 1p + V 2n (EQ. 7)
REP RATE = 50kHz
V ISEN2 = V 2p + V 1n
(EQ. 8)
The ISL62882 will make VISEN1 = VISEN2. So there are:
V 1p + V 2n = V 2p + V 1n (EQ. 9)
REP RATE = 100kHz
Rewriting Equation 9 gives:
V 1p - V 1n = V 2p - V 2n (EQ. 10)
Therefore:
R dcr1 x I L1 = R dcr2 x I L2 (EQ. 11)
Current balancing (IL1 = IL2) will be achieved when there is Rdcr1 = Rdcr2. Rpcb1 and Rpcb2 will not have any effect. Since the slave ripple capacitor voltages mimic the inductor currents, R3TM modulator can naturally achieve excellent current balancing during steady state and dynamic operations. Figure 15 shows current balancing performance of the ISL62882 evaluation board with load transient of 15A/50A at different rep rates. The inductor currents follow the load current dynamic change with the output capacitors supplying the difference. The inductor currents can track the load current well at a low rep rate, but cannot keep up when the rep rate gets into the hundred-kHz range, where it's out of the control loop bandwidth. The controller achieves excellent current balancing in all cases.
REP RATE = 200kHz
FIGURE 15. ISL62882 EVALUATION BOARD CURRENT BALANCING DURING DYNAMIC OPERATION. Ch1: IL1, Ch2: IIoad, Ch3: IL2
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CCM Switching Frequency
The Rfset resistor between the COMP and the VW pins sets the VW windows size, therefore sets the switching frequency. When the ISL62882 is in continuous conduction mode (CCM), the switching frequency is not absolutely constant due to the nature of the R3TM modulator. As explained in the "Multiphase R3TM Modulator" on page 12, the effective switching frequency will increase during load insertion and will decrease during load release to achieve fast response. On the other hand, the switching frequency is relatively constant at steady state. Variation is expected when the power stage condition, such as input voltage, output voltage, load, etc. changes. The variation is usually less than 15% and doesn't have any significant effect on output voltage ripple magnitude. Equation 12 gives an estimate of the frequency-setting resistor Rfset value. 8k Rfset gives approximately 300kHz switching frequency. Lower resistance gives higher switching frequency.
R fset ( k ) = ( Period ( s ) - 0.29 ) x 2.65 (EQ. 12)
If ISEN2 is tied to 5V, the ISL62882 is configured for 1-phase operation. Rbias = 147k sets 1-phase CPU VR configuration and Rbias=47k sets 1-phase GPU configuration. Table 3 shows the ISL62882 operational modes, programmed by the logic status of the PSI# and DPRSLPVR pins. In 2-phase configuration, the ISL62882 enters 1-phase CCM for (PSI# = 0 and DPRSLPVR = 0). It drops phase 2 and reduces the overcurrent and the way-overcurrent protection levels to 1/2 of the initial values. The ISL62882 enters 1-phase DE mode when DPRSLPVR = 1 by dropping phase 2. In 1-phase configuration, the ISL62882 does not change the operational mode when the PSI# signal changes status. It enters 1-phase DE mode when DLPRSLPVR = 1.
Dynamic Operation
When the ISL62882 is configured for CPU VR application, it responds to VID changes by slewing to the new voltage at 5mV/s slew rate. As the output approaches the VID command voltage, the dv/dt moderates to prevent overshoot. Geyserville-III transitions commands one LSB VID step (12.5mV) every 2.5s, controlling the effective dv/dt at 5mv/s. The ISL62882 is capable of 5mV/s slew rate. When the ISL62882 is configured for GPU VR application, it responds to VID changes by slewing to the new voltage at a slew rate set by the logic status on the DPRSLPVR pin. The slew rate is 5mV/s when DPRSLPVR=0 and is doubled when DPRSLPVR = 1. When the ISL62882 is in DE mode, it will actively drive the output voltage up when the VID changes to a higher value. It'll resume DE mode operation after reaching the new voltage level. If the load is light enough to warrant DCM, it will enter DCM after the inductor current has crossed zero for four consecutive cycles. The ISL62882 will remain in DE mode when the VID changes to a lower value. The output voltage will decay to the new value and the load will determine the slew rate. Over-voltage protection is blanked during VID down transition in DE mode until the output voltage is within 60mV of the VID value. During load insertion response, the Fast Clock function increases the PWM pulse response speed. The ISL62882 monitors the VSEN pin voltage and compares it to 100ns-filtered version. When the unfiltered version is 20mV below the filtered version, the controller knows there is a fast voltage dip due to load insertion, hence issues an additional master clock signal to deliver a PWM pulse immediately. The R3TM modulator intrinsically has voltage feedforward. The output voltage is insensitive to a fast slew rate input voltage change.
Modes of Operation
TABLE 2. ISL62882 CONFIGURATIONS Rbias (k) 147 47 147 47 1-phase CPU VR 1-phase GPU VR OVERSHOOT REDUCTION CONFIGURATION FUNCTION 2-phase CPU VR Disabled Enabled See Table 4
ISEN2 Connected to the Power Stage Tied to 5V
TABLE 3. ISL62882 MODES OF OPERATION VOLTAGE SLEW OPERATIONAL RATE PSI# DPRSLPVR MODE 0 0 1 1 1-phase CPU Configuration 1-phase GPU Configuration x x 0 1 0 1 0 1 0 1 1-phase CCM 1-phase DE 2-phase CCM 1-phase DE 1-phase CCM 1-phase DE 1-phase CCM 1-phase DE 10mV/s 5mV/s
CONFIG. 2-phase CPU Configuration
The ISL62882 can be configured for 2- or 1-phase operation. For 1-phase configuration, tie the ISEN2 pin to 5V. In this configuration, only phase-1 is active. Table 2 shows the ISL62882 configurations, programmed by the ISEN2 pin status and the Rbias value. If the ISEN2 pin is connected to the power stage, the ISL62882 is in 2-phase CPU VR configuration. Rbias = 147k disables the overshoot reduction function and Rbias = 47k enables it. 18
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Protections
The ISL62882 provides overcurrent, current-balance, undervoltage, overvoltage, and over-temperature protections. The ISL62882 determines overcurrent protection (OCP) by comparing the average value of the droop current Idroop with an internal current source threshold. It declares OCP when Idroop is above the threshold for 120s. A resistor Rcomp from the COMP pin to GND programs the OCP current source threshold, as well as the overshoot reduction function in 1-phase configuration, as Table 4 shows. It is recommended to use the nominal Rcomp value. The ISL62882 detects the Rcomp value at the beginning of start-up, and sets the internal OCP threshold accordingly. It remembers the Rcomp value until the VR_ON signal drops below the POR threshold.
TABLE 4. ISL62882 Rcomp PROGRAMABILITY Rcomp MIN NOMINAL MAX (k) (k) (k) none 320 210 155 104 78 62 45 400 235 165 120 85 66 50 none 480 260 175 136 92 70 55 2-PHASE CONFIG. 1-PHASE CONFIG. OVERSHOOT REDUCTION FUNCTION Disabled
The ISL62882 takes the same actions for all of the above fault protections: de-assertion of PGOOD and turn-off of the high-side and low-side power MOSFETs. Any residual inductor current will decay through the MOSFET body diodes. These fault conditions can be reset by bringing VR_ON low or by bringing VDD below the POR threshold. When VR_ON and VDD return to their high operating levels, a soft-start will occur. The second level of overvoltage protection is different. If the output voltage exceeds 1.55V, the ISL62882 will immediately declare an OV fault, de-assert PGOOD, and turn on the low-side power MOSFETs. The low-side power MOSFETs remain on until the output voltage is pulled down below 0.85V when all power MOSFETs are turned off. If the output voltage rises above 1.55V again, the protection process is repeated. This behavior provides the maximum amount of protection against shorted high-side power MOSFETs while preventing output ringing below ground. Resetting VR_ON cannot clear the 1.55V OVP. Only resetting VDD will clear it. The 1.55V OVP is active all the time when the controller is enabled, even if one of the other faults have been declared. This ensures that the processor is protected against high-side power MOSFET leakage while the MOSFETs are commanded off. The ISL62882 has a thermal throttling feature. If the voltage on the NTC pin goes below the 1.18V OT threshold, the VR_TT# pin is pulled low indicating the need for thermal throttling to the system. No other action is taken within the ISL62882 in response to NTC pin voltage. Table 5 summarizes the fault protections.
TABLE 5. FAULT PROTECTION SUMMARY FAULT DURATION BEFORE PROTECTION PROTECTION ACTION 120s <2s 1ms
OCP THRESHOLD (A) 40 45.3 41.3 36 37.33 38.7 42.7 44 20 22.7 20.7 18 20 22.7 20.7 18
Enabled
The default OCP threshold is the value when Rcomp is not populated. It is recommended to scale the droop current Idroop such that the default OCP threshold gives approximately the desired OCP level, then use Rcomp to fine tune the OCP level if necessary. For overcurrent conditions above 2.5x the OCP level, the PWM outputs will immediately shut off and PGOOD will go low to maximize protection. This protection is also referred to as way-overcurrent protection or fastovercurrent protection, for short-circuit protections. The ISL62882 monitors the ISEN pin voltages to determine current-balance protection. If the ISEN pin voltage difference is greater than 9mV for 1ms, the controller will declare a fault and latch off. The ISL62882 will declare undervoltage (UV) fault and latch off if the output voltage is less than the VID set value by 300mV or more for 1ms. It'll turn off the PWM outputs and de-assert PGOOD. The ISL62882 has two levels of overvoltage protections. The first level of overvoltage protection is referred to as PGOOD overvoltage protection. If the output voltage exceeds the VID set value by +200mV for 1ms, the ISL62882 will declare a fault and de-assert PGOOD. 19
FAULT TYPE Overcurrent Way-Overcurrent (2.5xOC) Overvoltage +200mV Undervoltage 300mV Phase Current Unbalance Overvoltage 1.55V
FAULT RESET
PWM tri-state, VR_ON toggle or PGOOD VDD latched low toggle
Immediately Low-side VDD MOSFET on toggle until Vcore <0.85V, then PWM tri-state, PGOOD latched low. 1ms N/A
Over-Temperature
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Current Monitor
The ISL62882 provides the current monitor function. The IMON pin outputs a high-speed analog current source that is 3 times of the droop current flowing out of the FB pin. Thus Equation 13:
I IMON = 3 x I droop (EQ. 13)
As Figures 1 and 2 show, a resistor Rimon is connected to the IMON pin to convert the IMON pin current to voltage. A capacitor can be paralleled with Rimon to filter the voltage information. The IMVP-6.5TM specification requires that the IMON voltage information be referenced to VSSSENSE. The IMON pin voltage range is 0V to 1.1V. A clamp circuit prevents the IMON pin voltage from going above 1.1V.
compares it with a threshold to determine the zero-crossing point of the inductor current. If the inductor current has not reached zero when the low-side MOSFET turns off, it'll flow through the low-side MOSFET body diode, causing the phase node to have a larger voltage drop until it decays to zero. If the inductor current has crossed zero and reversed the direction when the low-side MOSFET turns off, it'll flow through the highside MOSFET body diode, causing the phase node to have a spike until it decays to zero. The controller continues monitoring the phase voltage after turning off the low-side MOSFET and adjusts the phase comparator threshold voltage accordingly in iterative steps such that the low-side MOSFET body diode conducts for approximately 40ns to minimize the body diode-related loss.
FB2 Function
The FB2 function is only available when the ISL62882 is in 2-phase configuration.
CONTROLLER IN 2-PHASE MODE C1 R2 C3.1 C2 R3 R1 VSEN FB VREF E/A COMP FB VREF E/A COMP FB2 C3.2 C2 R3 R1 FB2 CONTROLLER IN 1-PHASE MODE C1 R2 C3.1 C3.2
Overshoot Reduction Function
The ISL62882 has an optional overshoot reduction function. Tables 2 and 4 show to enable and disable it. When a load release occurs, the energy stored in the inductors will dump to the output capacitor, causing output voltage overshoot. The inductor current freewheels through the low-side MOSFET during this period of time. The overshoot reduction function turns off the low-side MOSFET during the output voltage overshoot, forcing the inductor current to freewheel through the low-side MOSFET body diode. Since the body diode voltage drop is much higher than MOSFET Rdson voltage drop, more energy is dissipated on the low-side MOSFET therefore the output voltage overshoot is lower. If the overshoot reduction function is enabled, the ISL62882 monitors the COMP pin voltage to determine the output voltage overshoot condition. The COMP voltage will fall and hit the clamp voltage when the output voltage overshoots. The ISL62882 will turn off LGATE1 and LGATE2 when COMP is being clamped. All the low-side MOSFETs in the power stage will be turned off. When the output voltage has reached its peak and starts to come down, the COMP voltage starts to rise and is no longer clamped. The ISL62882 will resume normal PWM operation. When PSI# is low, indicating a low power state of the CPU, the controller will disable the overshoot reduction function as large magnitude transient event is not expected and overshoot is not a concern. While the overshoot reduction function reduces the output voltage overshoot, energy is dissipated on the low-side MOSFET, causing additional power loss. The more frequent transient event, the more power loss dissipated on the low-side MOSFET. The MOSFET may face severe thermal stress when transient events happen at a high repetitive rate. User discretion is advised when this function is enabled.
VSEN
FIGURE 16. FB2 FUNCTION IN 2-PHASE MODE
Figure 16 shows the FB2 function. A switch (called FB2 switch) turns on to short the FB and the FB2 pins when the controller is in 2-phase mode. Capacitors C3.1 and C3.2 are in parallel, serving as part of the compensator. When the controller enters 1-phase mode, the FB2 switch turns off, removing C3.2 and leaving only C3.1 in the compensator. The compensator gain will increase with the removal of C3.2. By properly sizing C3.1 and C3.2, the compensator cab be optimal for both 2-phase mode and 1-phase mode. When the FB2 switch is off, C3.2 is disconnected from the FB pin. However, the controller still actively drives the FB2 pin voltage to follow the FB pin voltage such that C3.2 voltage always follows C3.1 voltage. When the controller turns on the FB2 switch, C3.2 will be reconnected to the compensator smoothly. The FB2 function ensures excellent transient response in both 2-phase mode and 1-phase mode. If one decides not to use the FB2 function, simply populate C3.1 only.
Adaptive Body Diode Conduction Time Reduction
In DCM, the controller turns off the low-side MOSFET when the inductor current approaches zero. During ontime of the low-side MOSFET, phase voltage is negative and the amount is the MOSFET rDS(ON) voltage drop, which is proportional to the inductor current. A phase comparator inside the controller monitors the phase voltage during on-time of the low-side MOSFET and
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Key Component Selection
RBIAS The ISL62882 uses a resistor (1% or better tolerance is recommended) from the RBIAS pin to GND to establish highly accurate reference current sources inside the IC. Refer to Table 2 to select the resistance according to desired configuration. Do not connect any other components to this pin. Do not connect any capacitor to the RBIAS pin as it will create instability.
Care should be taken in layout that the resistor is placed very close to the RBIAS pin and that a good quality signal ground is connected to the opposite side of the RBIAS resistor.
actual board layout, which is why one cannot simply short them together for the current-sensing summing network. It is recommended to use 1~10 Ro to create quality signals. Since Ro value is much smaller than the rest of the current sensing circuit, the following analysis will ignore it for simplicity. The summed inductor current information is presented to the capacitor Cn. Equations 14 thru 18 describe the frequency-domain relationship between inductor total current Io(s) and Cn voltage VCn(s).
R ntcnet DCR V Cn ( s ) = ------------------------------------------ x ------------- x I o ( s ) x A cs ( s ) N R sum R ntcnet + ------------- N ( R ntcs + R ntc ) x R p R ntcnet = ---------------------------------------------------R ntcs + R ntc + R p s1 + -----L A cs ( s ) = ---------------------s 1 + ----------- sns DCR L = ------------L (EQ. 14)
Ris and Cis
As Figures 1 thru 4 show, the ISL62882 needs the Ris - Cis network across the ISUM+ and the ISUM- pins to stabilize the droop amplifier. The preferred values are Ris = 82.5 and Cis = 0.01F. Slight deviations from the recommended values are acceptable. Large deviations may result in instability.
(EQ. 15)
(EQ. 16)
Inductor DCR Current-Sensing Network
Phase1 Phase2 Rsum Rsum ISUM+
(EQ. 17)
L
L
Rntcs Rp Cn Vcn
1 sns = -------------------------------------------------------R sum R ntcnet x -------------N ------------------------------------------ x C n R sum R ntcnet + -------------N
(EQ. 18)
where N is the number of phases. Transfer function Acs(s) always has unity gain at DC. The inductor DCR value increases as the winding temperature increases, giving higher reading of the inductor DC current. The NTC Rntc values decreases as its temperature decreases. Proper selections of Rsum, Rntcs, Rp and Rntc parameters ensure that VCn represent the inductor total DC current over the temperature range of interest. There are many sets of parameters that can properly temperature-compensate the DCR change. Since the NTC network and the Rsum resistors form a voltage divider, Vcn is always a fraction of the inductor DCR voltage. It is recommended to have a higher ratio of Vcn to the inductor DCR voltage, so the droop circuit has higher signal level to work with. A typical set of parameters that provide good temperature compensation are: Rsum = 3.65k, Rp = 11k, Rntcs = 2.61k and Rntc = 10k (ERT-J1VR103J). The NTC network parameters may need to be fine tuned on actual boards. One can apply full load DC current and record the output voltage reading immediately; then record the output voltage reading again when the board has reached the thermal steady state. A good NTC network can limit the output voltage drift to within 2mV. It is recommended to follow the Intersil evaluation
DCR
DCR
Rntc Ro Ro Ri ISUM-
Io
FIGURE 17. DCR CURRENT-SENSING NETWORK
Figure 17 shows the inductor DCR current-sensing network for a 2-phase solution. An inductor current flows through the DCR and creates a voltage drop. Each inductor has two resistors in Rsum and Ro connected to the pads to accurately sense the inductor current by sensing the DCR voltage drop. The Rsum and Ro resistors are connected in a summing network as shown, and feed the total current information to the NTC network (consisting of Rntcs, Rntc and Rp) and capacitor Cn. Rntc is a negative temperature coefficient (NTC) thermistor, used to temperature-compensate the inductor DCR change. The inductor output side pads are electrically shorted in the schematic, but have some parasitic impedance in
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board layout and current-sensing network parameters to minimize engineering time. VCn(s) also needs to represent real-time Io(s) for the controller to achieve good transient response. Transfer function Acs(s) has a pole sns and a zero L. One needs to match L and sns so Acs(s) is unity gain at all frequencies. By forcing L equal to sns and solving for the solution, Equation 19 gives Cn value.
L C n = -------------------------------------------------------------R sum R ntcnet x -------------N ------------------------------------------ x DCR R sum R ntcnet + -------------N (EQ. 19)
upon load insertion and may create a system failure. Figure 20 shows the transient response when Cn is too large. Vcore is sluggish in drooping to its final value. There will be excessive overshoot if load insertion occurs during this time, which may potentially hurt the CPU reliability.
io
iL
Vo RING BACK
io
FIGURE 21. OUTPUT VOLTAGE RING BACK PROBLEM
Vo
ISUM+
FIGURE 18. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
io
Rntcs Rp Rntc
Cn.1 Cn.2 Vcn Rn Ri ISUM-
OPTIONAL
V o
Rip
Cip
FIGURE 19. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO SMALL
io
OPTIONAL
FIGURE 22. OPTIONAL CIRCUITS FOR RING BACK REDUCTION
V o
FIGURE 20. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO LARGE
For example, given N = 2, Rsum = 3.65k, Rp = 11k, Rntcs = 2.61k, Rntc = 10k, DCR = 0.88m and L = 0.36H, Equation 19 gives Cn = 0.294F. Assuming the compensator design is correct, Figure 18 shows the expected load transient response waveforms if Cn is correctly selected. When the load current Icore has a square change, the output voltage Vcore also has a square response. If Cn value is too large or too small, VCn(s) will not accurately represent real-time Io(s) and will worsen the transient response. Figure 19 shows the load transient response when Cn is too small. Vcore will sag excessively 22
Figure 21 shows the output voltage ring back problem during load transient response. The load current io has a fast step change, but the inductor current iL cannot accurately follow. Instead, iL responds in first order system fashion due to the nature of current loop. The ESR and ESL effect of the output capacitors makes the output voltage Vo dip quickly upon load current change. However, the controller regulates Vo according to the droop current idroop, which is a real-time representation of iL; therefore it pulls Vo back to the level dictated by iL, causing the ring back problem. This phenomenon is not observed when the output capacitor have very low ESR and ESL, such as all ceramic capacitors. Figure 22 shows two optional circuits for reduction of the ring back. Cn is the capacitor used to match the inductor time constant. It usually takes the parallel of two (or more) capacitors to get the desired value. Figure 22 shows that two capacitors Cn.1 and Cn.2 are in parallel. Resistor Rn is an optional component to reduce the Vo ring back. At steady state, Cn.1 + Cn.2 provides the desired Cn
FN6890.2 April 29, 2010
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capacitance. At the beginning of io change, the effective capacitance is less because Rn increases the impedance of the Cn.1 branch. As Figure 19 explains, Vo tends to dip when Cn is too small, and this effect will reduce the Vo ring back. This effect is more pronounced when Cn.1 is much larger than Cn.2. It is also more pronounced when Rn is bigger. However, the presence of Rn increases the ripple of the Vn signal if Cn.2 is too small. It is recommended to keep Cn.2 greater than 2200pF. Rn value usually is a few ohms. Cn.1, Cn.2 and Rn values should be determined through tuning the load transient response waveforms on an actual board. Rip and Cip form an R-C branch in parallel with Ri, providing a lower impedance path than Ri at the beginning of io change. Rip and Cip do not have any effect at steady state. Through proper selection of Rip and Cip values, idroop can resemble io rather than iL, and Vo will not ring back. The recommended value for Rip is 100. Cip should be determined through tuning the load transient response waveforms on an actual board. The recommended range for Cip is 100pF~2000pF. However, it should be noted that the Rip -Cip branch may distort the idroop waveform. Instead of being triangular as the real inductor current, idroop may have sharp spikes, which may adversely affect idroop average value detection and therefore may affect OCP accuracy. User discretion is advised.
1 A Rsen ( s ) = ---------------------s 1 + ----------- sns 1 Rsen = ---------------------------R sum -------------- x C n N (EQ. 21)
(EQ. 22)
Transfer function ARsen(s) always has unity gain at DC. Current-sensing resistor Rsen value will not have significant variation over-temperature, so there is no need for the NTC network. The recommended values are Rsum = 1k and Cn = 5600pF.
Overcurrent Protection
Refer to Equation 1 on page 16 and Figures 12, 17 and 23; resistor Ri sets the droop current Idroop. Table 4 shows the internal OCP threshold. It is recommended to design Idroop without using the Rcomp resistor. For example, the OCP threshold is 40A for 2-phase solution. We will design Idroop to be 34.3A at full load, so the OCP trip level is 1.16x of the full load current. For inductor DCR sensing, Equation 23 gives the DC relationship of Vcn(s) and Io(s).
R ntcnet DCR ------------------------------------------ x ------------- x I o V Cn = R sum N R ntcnet + ------------- N (EQ. 23)
Resistor Current-Sensing Network
PHASE1 PHASE2
Substitution of Equation 23 into Equation 1 gives Equation 24:
L L
R ntcnet DCR 2 I droop = ---- x ------------------------------------------ x ------------- x I o R sum N Ri R ntcnet + -------------N
(EQ. 24)
DCR
DCR RSUM RSUM ISUM+
Therefore:
2R ntcnet x DCR x I o R i = --------------------------------------------------------------------------------R sum N x R ntcnet + -------------- x I droop N (EQ. 25)
RSEN
RSEN RO RO
VCN
CN RI
ISUM-
Substitution of Equation 15 and application of the OCP condition in Equation 25 gives Equation 26:
( R ntcs + R ntc ) x R p 2 x ---------------------------------------------------- x DCR x I omax R ntcs + R ntc + R p R i = ---------------------------------------------------------------------------------------------------------------------------( R ntcs + R ntc ) x R p R sum N x ---------------------------------------------------- + -------------- x I droopmax N R ntcs + R ntc + R p
(EQ. 26)
IO
FIGURE 23. RESISTOR CURRENT-SENSING NETWORK
Figure 23 shows the resistor current-sensing network for a 2-phase solution. Each inductor has a series currentsensing resistor Rsen. Rsum and Ro are connected to the Rsen pads to accurately capture the inductor current information. The Rsum and Ro resistors are connected to capacitor Cn. Rsum and Cn form a a filter for noise attenuation. Equations 20 thru 22 give VCn(s) expression
R sen V Cn ( s ) = ------------- x I o ( s ) x A Rsen ( s ) N (EQ. 20)
where Iomax is the full load current, Idroopmax is the corresponding droop current. For example, given N = 2, Rsum = 3.65k, Rp = 11k, Rntcs = 2.61k, Rntc = 10k, DCR = 0.88m, Iomax = 51A and Idroopmax = 34.3A, Equation 26 gives Ri = 998. For resistor sensing, Equation 27 gives the DC relationship of Vcn(s) and Io(s).
R sen V Cn = ------------- x I o N (EQ. 27)
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Substitution of Equation 27 into Equation 1 gives Equation 28:
2 R sen I droop = ---- x ------------- x I o N Ri (EQ. 28)
Current Monitor
Refer to Equation 13 for the IMON pin current expression. Refer to Figures 1 and 2, the IMON pin current flows through Rimon. The voltage across Rimon is expressed in Equation 34:
V Rimon = 3 x I droop x R imon (EQ. 34)
Therefore
2R sen x I o R i = --------------------------N x I droop (EQ. 29)
Substitution of Equation 29 and application of the OCP condition in Equation 25 gives Equation 30:
2R sen x I omax R i = --------------------------------------N x I droopmax (EQ. 30)
Rewriting Equation 33 gives Equation 35:
Io I droop = ------------------ x LL R droop (EQ. 35)
where Iomax is the full load current, Idroopmax is the corresponding droop current. For example, given N = 2, Rsen = 1m, Iomax = 51A and Idroopmax = 34.3A, Equation 30 gives Ri = 1.487k. A resistor from COMP to GND can adjust the internal OCP threshold, providing another dimension of fine-tune flexibility. Table 4 shows the detail. It is recommended to scale Idroop such that the default OCP threshold gives approximately the desired OCP level, then use Rcomp to fine tune the OCP level if necessary.
Substitution of Equation 35 into Equation 34 gives Equation 36:
3I o x LL V Rimon = --------------------- x R imon R droop (EQ. 36)
Rewriting Equation 36 and application of full load condition gives Equation 37:
V Rimon x R droop R imon = ---------------------------------------------3I o x LL (EQ. 37)
Load Line Slope
Refer to Figure 12. For inductor DCR sensing, substitution of Equation 24 into Equation 2 gives the load line slope expression:
2R droop R ntcnet V droop DCR LL = ------------------ = ---------------------- x ------------------------------------------ x ------------N Io Ri R sum R ntcnet + -------------N (EQ. 31)
For example, given LL = 1.9m, Rdroop = 2.825k, VRimon = 963mV at Iomax = 51A, Equation 37 gives Rimon = 9.358k. A capacitor Cimon can be paralleled with Rimon to filter the IMON pin voltage. The RimonCimon time constant is the user's choice. It is recommended to have a time constant long enough such that switching frequency ripples are removed.
Compensator
Figure 18 shows the desired load transient response waveforms. Figure 24 shows the equivalent circuit of a voltage regulator (VR) with the droop function. A VR is equivalent to a voltage source (= VID) and output impedance Zout(s). If Zout(s) is equal to the load line slope LL, i.e. constant output impedance, in the entire frequency range, Vo will have square response when Io has a square change.
Zout(s) = LL i o
For resistor sensing, substitution of Equation 28 into Equation 2 gives the load line slope expression:
2R sen x R droop V droop LL = ------------------ = -----------------------------------------Io N x Ri (EQ. 32)
Substitution of Equation 25 and rewriting Equation 31, or substitution of Equation 29 and rewriting Equation 32 give the same result in Equation 33:
Io R droop = ---------------- x LL I droop (EQ. 33)
One can use the full load condition to calculate Rdroop. For example, given Iomax = 51A, Idroopmax = 34.3A and LL = 1.9m, Equation 33 gives Rdroop = 2.825k. It is recommended to start with the Rdroop value calculated by Equation 33, and fine tune it on the actual board to get accurate load line slope. One should record the output voltage readings at no load and at full load for load line slope calculation. Reading the output voltage at lighter load instead of full load will increase the measurement error.
VID
VR
LOAD
V o
FIGURE 24. VOLTAGE REGULATOR EQUIVALENT
Intersil provides a Microsoft Excel-based spreadsheet to help design the compensator and the current sensing network, so the VR achieves constant output impedance as a stable system. Figure 27 shows a screenshot of the spreadsheet.
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A VR with active droop function is a dual-loop system consisting of a voltage loop and a droop loop which is a current loop. However, neither loop alone is sufficient to describe the entire system. The spreadsheet shows two loop gain transfer functions, T1(s) and T2(s), that describe the entire system. Figure 25 conceptually shows T1(s) measurement set-up and Figure 26 conceptually shows T2(s) measurement set-up. The VR senses the inductor current, multiplies it by a gain of the load line slope, then adds it on top of the sensed output voltage and feeds it to the compensator. T(1) is measured after the summing node, and T2(s) is measured in the voltage loop before the summing node. The spreadsheet gives both T1(s) and T2(s) plots. However, only T2(s) can be actually measured on an ISL62882 regulator. T1(s) is the total loop gain of the voltage loop and the droop loop. It always has a higher crossover frequency than T2(s) and has more meaning of system stability. T2(s) is the voltage loop gain with closed droop loop. It has more meaning of output voltage response. Design the compensator to get stable T1(s) and T2(s) with sufficient phase margin, and output impedance equal or smaller than the load line slope.
Q1 VIN GATE Q2 DRIVER COUT I O
L Q1 Vin GATE Q2 DRIVER C out
V o
io
LOAD LINE SLOPE 20 MOD. COMP CHANNEL B LOOP GAIN = CHANNEL A EA VID ISOLATION TRANSFORMER
CHANNEL A CHANNEL B NETWORK ANALYZER EXCITATION OUTPUT
FIGURE 25. LOOP GAIN T1(s) MEASUREMENT SET-UP
L
V O
LOAD LINE SLOPE 20 MOD. COMP CHANNEL B LOOP GAIN= CHANNEL A EA VID ISOLATION TRANSFORMER
CHANNEL A CHANNEL B NETWORK ANALYZER EXCITATION OUTPUT
FIGURE 26. LOOP GAIN T2(s) MEASUREMENT SET-UP
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FN6890.2 April 29, 2010
Compensation & Current Sensing Network Design for Intersil Multiphase R^3 Regulators for IMVP-6.5
Jia Wei, jwei@intersil.com, 919-405-3605 Attention: 1. "Analysis ToolPak" Add-in is required. To turn on, go to Tools--Add-Ins, and check "Analysis ToolPak". 2. Green cells require user input Compensator Parameters Operation Parameters Controller Part Number: ISL6288x s * s* 1 KZi Zi 1 Phase Number: 2 2Sf z1 2Sf z 2 (c) (c) AV ( s ) Vin: 12 volts s * s* 1 Vo: 1.15 volts s 1 2Sf p1 2Sf p 2 (c) (c) Full Load Current: 50 Amps Estimated Full-Load Efficiency: 87 % Number of Output Bulk Capacitors: 3 Recommended Value User-Selected Value Capacitance of Each Output Bulk Capacitor: 470 uF R1 2.870 k : R1 2.87 k : ESR of Each Output Bulk Capacitor: 4.5 m : ESL of Each Output Bulk Capacitor: 0.6 nH R2 387.248 k : R2 412 k : Number of Output Ceramic Capacitors: 30 R3 0.560 k : R3 0.562 k : Capacitance of Each Output Ceramic Capacitor: 10 uF C1 188.980 pF C1 150 pF C2 498.514 pF C2 390 pF ESR of Each Output Ceramic Capacitor: 3 m: ESL of Each Output Ceramic Capacitor: 3 nH C3 32.245 pF C3 32 pF Switching Frequency: 300 kHz Use User-Selected Value (Y/N)? N Inductance Per Phase: 0.36 uH CPU Socket Resistance: 0.9 m : Performance and Stability Desired Load-Line Slope: 1.9 m : Desired ISUM- Pin Current at Full Load: 33.1 uA T1 Bandwidth: 190kHz T2 Bandwidth: 52kHz (This sets the over-current protection level) T1 Phase Margin: 63.4 T2 Phase Margin: 94.7
Changing the settings in red requires deep understanding of control loop design Place the 2nd compensator pole fp2 at: 1.9 xfs (Switching Frequency) Tune K i to get the desired loop gain bandwidth
Current Sensing Network Parameters
0DJQLWXGH PRKP
*DLQ G%
3KDVH GHJUHH
3KDVH GHJUHH
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FN6890.2 April 29, 2010
ISL62882, ISL62882B
Tune the compensator gain factor K i: (Recommended K i range is 0.8~2) ( ( ( ( )UHTXHQF\ +]
1.15
Output Impedance, Gain Curve
Operation Parameters Inductor DCR 0.88 m : Rsum 3.65 k : Rntc 10 k : Rntcs 2.61 k : Rp 11 k : Recommended Value Cn 0.294 uF Ri 1014.245 : User Selected Value Cn 0.294 uF Ri 1000 :
Loop Gain, Gain Curve 7V 7V
(
(
(
(
(
(
(
(
)UHTXHQF\ +] Output Impedance, Phase Curve
(
Loop Gain, Phase Curve 7V 7V
(
(
( ( )UHTXHQF\ +]
(
(
(
( ( )UHTXHQF\ +]
(
(
FIGURE 27. SCREENSHOT OF THE COMPENSATOR DESIGN SPREADSHEET
ISL62882, ISL62882B
Optional Slew Rate Compensation Circuit For 1-Tick VID Transition
Rdroop Vcore Rvid Cvid OPTIONAL FB Ivid Idroop_vid E/A COMP
To control Vcore slew rate during 1-tick VID transition, one can add the Rvid-Cvid branch, whose current Ivid cancels Idroop_vid. When Vcore increases, the time domain expression of the induced Idroop change is
-------------------------- C out x LL dV core C x LL I droop ( t ) = ------------------------- x ------------------ x 1 - e out dt R droop -t
(EQ. 38)
where Cout is the total output capacitance.
VIDs VID<0:6> RTN VSSSENSE
VDACDAC
X1
In the mean time, the Rvid-Cvid branch current Ivid time domain expression is:
------------------------------- dV fb R xC vid I vid ( t ) = C vid x ------------ x 1 - e vid dt -t
(EQ. 39)
INTERNAL TO IC
VID<0:6>
VSS
It is desired to let Ivid(t) cancel Idroop_vid(t). So there are:
dV fb C out x LL dV core C vid x ------------ = ------------------------- x -----------------R droop dt dt (EQ. 40)
Vfb
and:
Ivid
R vid x C vid = C out x LL
(EQ. 41)
The result is expressed in Equation 42:
R vid = R droop
Vcore
(EQ. 42)
and:
dV core C out x LL -----------------dt C vid = ------------------------- x -----------------R droop dV fb -----------dt (EQ. 43)
Idroop_vid
FIGURE 28. OPTIONAL SLEW RATE COMPENSATION CIRCUIT FOR1-TICK VID TRANSITION
During a large VID transition, the DAC steps through the VIDs at a controlled slew rate. For example, the DAC may change a tick (12.5mV) per 2.5s per, controlling output voltage Vcore slew rate at 5mV/s. Figure 28 shows the waveforms of 1-tick VID transition. During 1-tick VID transition, the DAC output changes at approximately 15mV/s slew rate, but the DAC cannot step through multiple VIDs to control the slew rate. Instead, the control loop response speed determines Vcore slew rate. Ideally, Vcore will follow the FB pin voltage slew rate. However, the controller senses the inductor current increase during the up transition, as the Idroop_vid waveform shows, and will droop the output voltage Vcore accordingly, making Vcore slew rate slow. Similar behavior occurs during the down transition.
For example: given LL = 1.9m, Rdroop = 2.87k, Cout = 1710F, dVcore/dt = 5mV/s and dVfb/dt = 15mV/s, Equation 42 gives Rvid = 2.87k and Equation 43 gives Cvid = 377pF. It's recommended to select the calculated Rvid value and start with the calculated Cvid value and tweak it on the actual board to get the best performance. During normal transient response, the FB pin voltage is held constant, therefore is virtual ground in small signal sense. The Rvid - Cvid network is between the virtual ground and the real ground, and hence has no effect on transient response.
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Voltage Regulator Thermal Throttling
54A 64A
Therefore, a larger value thermistor such as 470k NTC should be used. At +105C, 470k NTC resistance becomes (0.03322 x 470k) = 15.6k. With 60A on the NTC pin, the voltage is only (15.6k x 60A) = 0.937V. This value is much lower than the threshold voltage of 1.20V. Therefore, a regular resistor needs to be in series with the NTC. The required resistance can be calculated by Equation 46:
1.20V --------------- - 15.6k = 4.4k 60A (EQ. 46)
SW1 NTC VNTC + RNTC Rs 1.24V SW2 1.20V INTERNAL TO ISL62882 +
VR_TT#
FIGURE 29. CIRCUITRY ASSOCIATED WITH THE THERMAL THROTTLING FEATURE OF THE ISL62882
4.42k is a standard resistor value. Therefore, the NTC branch should have a 470k NTC and 4.42k resistor in series. The part number for the NTC thermistor is ERTJ0EV474J. It is a 0402 package. NTC thermistor will be placed in the hot spot of the board.
Current Balancing
Refer to Figures 1 and 2. The ISL62882 achieves current balancing through matching the ISEN pin voltages. Rs and Cs form filters to remove the switching ripple of the phase node voltages. It is recommended to use rather long RsCs time constant such that the ISEN voltages have minimal ripple and represent the DC current flowing through the inductors. Recommended values are Rs = 10k and Cs = 0.22F.
Figure 29 shows the thermal throttling feature with hysteresis. An NTC network is connected between the NTC pin and GND. At low temperature, SW1 is on and SW2 connects to the 1.20V side. The total current flowing out of the NTC pin is 60A. The voltage on NTC pin is higher than threshold voltage of 1.20V and the comparator output is low. VR_TT# is pulled up by the external resistor. When temperature increases, the NTC thermistor resistance decreases so the NTC pin voltage drops. When the NTC pin voltage drops below 1.20V, the comparator changes polarity and turns SW1 off and throws SW2 to 1.24V. This pulls VR_TT# low and sends the signal to start thermal throttle. There is a 6A current reduction on NTC pin and 40mV voltage increase on threshold voltage of the comparator in this state. The VR_TT# signal will be used to change the CPU operation and decrease the power consumption. When the temperature drops down, the NTC thermistor voltage will go up. If NTC voltage increases to above 1.24V, the comparator will flip back. The external resistance difference in these two conditions is shown in Equation 44:
1.24V 1.20V --------------- - --------------- = 2.96k 54A 60A (EQ. 44)
Layout Guidelines
Table 6 shows the layout considerations. The designators refer to the reference design shown in Figure 31.
TABLE 6. LAYOUT CONSIDERATION PIN EP NAME GND LAYOUT CONSIDERATION Create analog ground plane underneath the controller and the analog signal processing components. Don't let the power ground plane overlap with the analog ground plane. Avoid noisy planes/traces (e.g.: phase node) from crossing over/overlapping with the analog plane. No special consideration No special consideration Place the RBIAS resistor (R16) in general proximity of the controller. Low impedance connection to the analog ground plane. No special consideration The NTC thermistor (R9) needs to be placed close to the thermal source that is monitor to determine thermal throttling. Usually it's placed close to phase-1 highside MOSFET. Place the capacitor (C4) across VW and COMP in close proximity of the controller Place the compensator components (C3, C5, C6 R7, R11, R10 and C11) in general proximity of the controller.
1 2 3
PGOOD PSI# RBIAS
One needs to properly select the NTC thermistor value such that the required temperature hysteresis correlates to 2.96k resistance change. A regular resistor may need to be in series with the NTC thermistor to meet the threshold voltage values. For example, given Panasonic NTC thermistor with B = 4700, the resistance will drop to 0.03322 of its nominal at +105C, and drop to 0.03956 of its nominal at +100C. If the required temperature hysteresis is +105C to +100C, the required resistance of NTC will be as shown in Equation 45:
2.96k ----------------------------------------------------- = 467k ( 0.03956 - 0.03322 ) (EQ. 45)
4 5
VR_TT# NTC
6 7 8 9
VW COMP FB FB2
28
FN6890.2 April 29, 2010
ISL62882, ISL62882B
TABLE 6. LAYOUT CONSIDERATION (Continued) PIN 10 NAME ISEN2 LAYOUT CONSIDERATION A capacitor (C9) decouples it to VSUM-. Place it in general proximity of the controller. A capacitor (C10) decouples it to VSUM-. Place it in general proximity of the controller. Place the VSEN/RTN filter (C12, C13) in close proximity of the controller for good decoupling. Place the current sensing circuit in general proximity of the controller. Place C82 very close to the controller. Place NTC thermistors R42 next to phase1 inductor (L1) so it senses the inductor temperature correctly. Each phase of the power stage sends a pair of VSUM+ and VSUM- signals to the controller. Run these two signals traces in parallel fashion with decent width (>20mil). IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. Route R63 and R71 to the phase-1 side pad of inductor L1. Route R88 to the output side pad of inductor L1. Route R65 and R72 to the phase-2 side pad of inductor L2. Route R90 to the output side pad of inductor L2. If possible, route the traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is allowed on the pad, consider routing the traces into the pads from the inside of the inductor. The following drawings show the two preferred ways of routing current sensing traces. 22 23 24 VSSP1 LGATE1a LGATE1b TABLE 6. LAYOUT CONSIDERATION (Continued) PIN 20 21 NAME UGATE1 PHASE1 LAYOUT CONSIDERATION Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close. Recommend routing PHASE1 trace to the phase-1 high-side MOSFET (Q2 and Q8) source pins instead of general phase-1 node copper. Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close. Recommend routing VSSP1 to the phase-1 low-side MOSFET (Q3 and Q9) source pins instead of general power ground plane for better performance. A capacitor (C22) decouples it to GND. Place it in close proximity of the controller. Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close. Recommend routing VSSP2 to the phase-2 low-side MOSFET (Q5 and Q1) source pins instead of general power ground plane for better performance. Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close. Recommend routing PHASE2 trace to the phase-2 high-side MOSFET (Q4 and Q10) source pins instead of general phase-2 node copper. Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close. No special consideration. No special consideration.
11
ISEN1
12 13 14 15
VSEN RTN ISUMISUM+
25 26 27
VCCP LGATE2 VSSP2
28 29
PHASE2 UGATE2
30
BOOT2
Inductor
Inductor
31~3 7 38 39 40 Other
VID0~6 VR_ON
DPRSLPVR No special consideration. CLK_EN# No special consideration. Phase Node Minimize phase node copper area. Don't let the phase node copper overlap with/getting close to other sensitive traces. Cut the power ground plane to avoid overlapping with phase node copper. Minimize the loop consisting of input capacitor, high-side MOSFETs and low-side MOSFETs (e.g.: C27, C33, Q2, Q8, Q3 and Q9).
Vias Current-Sensing Traces
16 17 18 19 VDD VIN IMON BOOT1
Current-Sensing Traces
A capacitor (C16) decouples it to GND. Place it in close proximity of the controller. A capacitor (C17) decouples it to GND. Place it in close proximity of the controller. Place the filter capacitor (C21) close to the CPU. Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
Other
29
FN6890.2 April 29, 2010
8
7
6
5
4
3
2
1
D
VR_ON DPRSLPVR +3.3V
VID0 VID1 VID2 VID3 VID4 VID5 VID6
IN IN IN IN IN IN IN IN IN IN
D
1.91K
R19
CLK_EN# DPRSLPVR VR_ON VID6 VID5 VID4 VID3 VID2 VID1 VID0
VIN
IN
10UF C33
PGOOD +1.1V
OUT IN
10UF
IRF7821
------------
499 -------
R12
OPTIONAL -----
56UF
C27
C24
PGOOD R16 PSI# RBIAS VR_TT# NTC VW COMP FB FB2 ISEN2 EP R20 U6 ISL62882HRZ
BOOT2 UGATE2 PHASE2
Q2 L1
------R4
DNP ------R6
C22
1UF
1000PF
----
22UF
22UF
22UF
22UF
22UF
22UF
22UF
C60
C59
C40
C56
C55
10K
----
DNP DNP ------------
C4
VCCP LGATE1B LGATE1A VSSP1 PHASE1
IN
+5V
Q3
Q9
--------
DNP DNP --------
C83 R110
OPTIONAL ----
C6 C3
R10 R7 R11
C11
15PF
2.37K 270PF 6.98K
C54
C61
C41
C52
LGATE2
22UF
C
IRF7832
IRF7832
470UF 4MOHM
----
100PF
422K
B
----C12
330PF 1000PF -----
VCORE
IN
R17 10
IN
OPTIONAL -------
0
ISEN1 VSEN RTN ISUMISUM+ VDD VIN IMON BOOT UGATE1
R50
0.22UF
VSSSENSE
IN
R18 10
1UF C17
C13
C16
0
C21
IN
22.6K
1
0.01UF
0.01UF 82.5
10K 2.61K NTC
0.056UF
R26
0.15UF
R41
R38
A
-----> R42
C15
11K
C82
C18
0.1UF
----
----
C20
30
FN6890.2 April 29, 2010
OPTIONAL ---- VR_TT#
IN
47.5K ------R8 R9
VSSP2
0.88UH 2.3MOHM
OUT
VCORE
C
ISL62882, ISL62882B
R56 0 R37 R40
IN
C30 0.22UF
OUT
B
VCCSENSE
+5V VIN
IMON
LAYOUT
IN
NOTE:
R63
VSSSENSE
3.65K
ROUTE UGATE TRACE IN PARALLEL WITH THE PHASE TRACE GOING TO THE SOURCE OF Q2 ROUTE LGATE TRACE IN PARALLEL WITH THE VSSP TRACE GOING TO THE SOURCE OF Q3
R30
A
3.01K -----------C81 R109 DNP DNP -----------OPTIONAL
PLACE NEAR L1
TITLE: ISL62881
FIGURE 30. 1-PHASE GPU APPLICATON REFERENCE DESIGN
8 7 6 5 4 3
GPU REFERENCE DESIGN 1-PHASE, DCR SENSING JIA WEI
2
DATE: PAGE:
3/16/2009 1 OF 1
1
ENGINEER:
8
7
6
5
4
IN
3
2
1
VIN VID0 IN VID1 IN VID2 IN VID3 IN VID4 IN VID5 IN VID6 IN VR_ON IN DPRSLPVR IN CLK_EN# OUT +3.3V
IN
10UF C34
10UF
56UF C25
56UF
C28
C24
IRF7821
IRF7821
Q4
Q10 L2 D
D
470UF
470UF
3.65K
R23 1.91K
10K R90
R65
R72
0
0.22UF
Q5
Q11
1
10UF
10UF
10UF
10UF
DNP 10UF 10UF
C39
C52
C57
C44
R57
C31
IRF7832
IRF7832
470UF
0.36UH
OUT
VCORE
CLK_EN# DPRSLPVR VR_ON VID6 VID5 VID4 VID3 VID2 VID1 VID0
1.91K
R19
VSUM+
ISEN2
10UF C33
10UF
C27
PSI# +1.1V
C
IN IN
VSUM-
10UF
C41
PGOOD OUT
10UF
10UF
10UF
PGOOD R16 R8 147K R9 PSI# RBIAS VR_TT# NTC VW COMP FB U6 ISL62882HRZ
BOOT2 UGATE2 PHASE2 VSSP2 LGATE2 VCCP LGATE1B LGATE1A VSSP1 PHASE1
IN
IRF7821
IRF7821
10UF
R12
499
C49
C50
C53
C54
C55
C56
10UF
C40
C42
C43
C47
C48
------R4
DNP ------R6
8.06K
10UF
10UF
10UF
10UF
10UF
1000PF
DNP
DNP
C4
3.65K
R63
R71
C5
10K R88
----
+5V
R56 0
C30 0.22UF
IRF7832
IRF7832
0.36UH
10UF
C62
C63
C59
C60
C64
C61
10UF
10UF
10UF
10UF
------------C83 R110
560PF 2.87K -------------
10UF
C6
R10
C11
FB2 ISEN2 EP
VSUM+
10UF
10UF
10UF
10UF
10UF
0.22UF
0.22UF
OPTIONAL ---ISEN2 IN ISEN1 IN
C9
LAYOUT NOTE:
1
C10
R50
0.22UF
C16
1UF C17
0
C21
0
IN
0.01UF
R20
R37 R40
OUT IN
9.31K
+5V VIN
IMON
ROUTE UGATE1 TRACE IN PARALLEL WITH THE PHASE1 TRACE GOING TO THE SOURCE OF Q2 AND Q8 ROUTE LGATE1 TRACE IN PARALLEL WITH THE VSSP1 TRACE GOING TO THE SOURCE OF Q3 AND Q9 SAME RULE APPLIES TO OTHER PHASES
A
----C12
1000PF 330PF ---------
0.33UF
IN IN
R38
C15
R18 10
R30
-----> R42
C13
VSSSENSE
11K
C82
C18
----
R41
VCCSENSE
R26
A
0.047UF
10
0.01UF 82.5
10K 2.61K NTC
VCORE
IN
R17
OPTIONAL ----
IN IN
VSSSENSE VSUM+
----
----
0.1UF
C20
1K ----------C81 R109 1200PF 100 ----------OPTIONAL
IN
VSUMTITLE:
PLACE NEAR L1
ISL62882 REFERENCE DESIGN 2-PHASE, DCR SENSING JIA WEI
2
DATE: PAGE:
JULY 2009 1 OF 1
1
ENGINEER: 8 7 6 4 3 FIGURE 31. 2-PHASE5 CPU APPLICATION REFERENCE DESIGN
10UF
C72
C73
C74
C75
C78
C71
B
150PF
412K
2.87K
ISEN1 VSEN RTN ISUMISUM+ VDD VIN IMON BOOT UGATE1
C22
1UF
C3
R7
R11
VSUM-
ISEN1
10PF
562
390PF
10UF
C65
C66
C67
C68
C69
C70
----
22PF
1
31
FN6890.2 April 29, 2010
OUT
OUT
OUT
VR_TT# OUT ---- OPTIONAL
Q2
Q8 L1
C
ISL62882, ISL62882B
Q3
Q9
OUT
OUT
OUT
B
ISL62882, ISL62882B
1-Phase GPU Application Reference Design Bill of Materials
QTY 1 1 1 1 2 1 1 3 1 2 1 1 REFERENCE C11 C12 C13 C15 C16,C22 C18 C20 C17, C21, C30 C24 C27,C33 C3 C52 VALUE 270pF 330pF DESCRIPTION Multilayer Cap, 16V, 10% Multilayer Cap, 16V, 10% MANUFACTURER GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC SANYO GENERIC GENERIC PANASONIC KEMET 1 8 C4 C40, C41, C54-C56, C59-C61 C6 C82 C81, C83 L1 Q2 Q3, Q9 R10 R11 R16 R17, R18 R19 R26 R20, R40, R56 R30 R37 R38 R41 R42 R50 2.37k 6.98k 47.5k 10 1.91k 82.5 0 3.01k 1 11k 2.61k 1000pF Multilayer Cap, 16V, 10% 10F Multilayer Cap, 6.3V, 20% GENERIC MURATA PANASONIC TDK GENERIC GENERIC H1065-00106-25V20 H1045-00101-16V10 EEXSX0D471E4 T520V477M2R5A(1)E4R 5-6666 H1045-00102-16V10 SM0603 SM1206 SM0603 PART NUMBER H1045-00271-16V10 H1045-00331-16V10 H1045-00102-16V10 H1045-00103-16V10 H1045-00105-16V20 H1045-00154-16V10 H1045-00104-16V10 H1045-00224-25V10 25SP56M PACKAGE SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 CASE-CC
1000pF Multilayer Cap, 16V, 10% 0.01F Multilayer Cap, 16V, 10% 1F Multilayer Cap, 16V, 20%
0.15F Multilayer Cap, 16V, 10% 0.1F Multilayer Cap, 16V, 10%
0.22F Multilayer Cap, 25V, 10% 56F 10F 100pF 470F Radial SP Series Cap, 25V, 20% Multilayer Cap, 25V, 20% Multilayer Cap, 16V, 10% SPCAP, 2V, 4M POLYMER CAP, 2.5V, 4.5M
GRM21BR61C106KE15L SM0805 ECJ2FB0J106K C2012X5R0J106K H1045-00150-16V10 H1045-00563-16V10 SM0603 SM0603
1 1 0 1 1 2 1 1 1 2 1 1 3 1 1 1 1 1 1
15pF
Multilayer Cap, 16V, 10%
0.056F Multilayer Cap, 16V, 10% DNP 0.88H Inductor, Inductance 20%, DCR 7% N-Channel Power MOSFET N-Channel Power MOSFET Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1%
MPC1040LR88 NEC-TOKIN IR IR GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC PANASONIC GENERIC IRF7821 IRF7832 H2511-02371-1/16W1 H2511-06981-1/16W1 H2511-04752-1/16W1 H2511-00100-1/16W1 H2511-01911-1/16W1 H2511-082R5-1/16W1 H2511-00R00-1/16W1 H2511-03011-1/16W1 H2511-01R00-1/16W1 H2511-01102-1/16W1 H2511-02611-1/16W1 ERT-J1VR103J H2511-02262-1/16W1
10mmx10mm PWRPAKSO8 PWRPAKSO8 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603
10k NTC Thermistor, 10k NTC 22.6k Thick Film Chip Resistor, 1%
32
FN6890.2 April 29, 2010
ISL62882, ISL62882B
1-Phase GPU Application Reference Design Bill of Materials (Continued)
QTY 1 1 1 0 1 REFERENCE R6 R63 R7 R109, R110, R4, R8, R9 U6 VALUE 10k 3.65k 412k DNP IMVP-6.5 PWM Controller INTERSIL ISL62882HRTZ QFN-40 DESCRIPTION Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% MANUFACTURER GENERIC GENERIC GENERIC PART NUMBER H2511-01002-1/16W1 H2511-03651-1/16W1 H2511-04123-1/16W1 PACKAGE SM0603 SM0805 SM0603
2-Phase CPU Application Reference Design Bill of Materials
QTY 1 1 1 2 2 1 1 5 2 4 1 3 REFERENCE C11 C12 C13 C15, C21 C16,C22 C18 C20 C9, C10, C17, C30, C31 C24,C25 C27,C28,C33,C34 C3 C39, C52, C57 VALUE 390pF 330pF DESCRIPTION Multilayer Cap, 16V, 10% Multilayer Cap, 16V, 10% MANUFACTURER GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC PART NUMBER H1045-00391-16V10 H1045-00331-16V10 H1045-00102-16V10 H1045-00103-16V10 H1045-00105-16V20 H1045-00334-16V10 H1045-00104-16V10 H1045-00224-25V10 25SP56M H1065-00106-25V20 H1045-00151-16V10 EEXSX0D471E4 T520V477M2R5A(1)E4R 5-6666 H1045-00102-16V10 SM0603 PACKAGE SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 CASE-CC SM1206 SM0603
1000pF Multilayer Cap, 16V, 10% 0.01F Multilayer Cap, 16V, 10% 1F Multilayer Cap, 16V, 20%
0.33F Multilayer Cap, 16V, 10% 0.1F Multilayer Cap, 16V, 10%
0.22F Multilayer Cap, 25V, 10% 56F 10F 150pF 470F
Radial SP Series Cap, 25V, 20% SANYO Multilayer Cap, 25V, 20% Multilayer Cap, 16V, 10% SPCAP, 2V, 4M POLYMER CAP, 2.5V, 4.5M GENERIC GENERIC PANASONIC KEMET GENERIC MURATA PANASONIC TDK GENERIC GENERIC GENERIC GENERIC GENERIC NEC-TOKIN PANASONIC IR IR GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC
1 30
C4 C40-C43, C47-C50, C53-C56, C59-C75, C78 C5 C6 C81 C82 C83 L1, L2 Q2, Q4, Q8, Q10 Q3, Q5, Q9, Q11 R10 R109 R11 R110 R12 R16
1000pF Multilayer Cap, 16V, 10% 10F Multilayer Cap, 6.3V, 20%
GRM21BR61C106KE15L SM0805 ECJ2FB0J106K C2012X5R0J106K H1045-00220-16V10 H1045-00100-16V10 H1045-00122-16V10 H1045-00473-16V10 H1045-00561-16V10 MPCH1040LR36 ETQP4LR36AFC IRF7821 IRF7832 H2511-05620-1/16W1 H2511-01000-1/16W1 H2511-02871-1/16W1 H2511-02871-1/16W1 H2511-04990-1/16W1 H2511-01473-1/16W1 SM0603 SM0603 SM0603 SM0603 SM0603 10mmx10mm PWRPAKSO8 PWRPAKSO8 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603
1 1 1 1 1 2 4 4 1 1 1 1 1 1
22pF 10pF
Multilayer Cap, 16V, 10% Multilayer Cap, 16V, 10%
1200pF Multilayer Cap, 16V, 10% 0.047F Multilayer Cap, 16V, 10% 560pF Multilayer Cap, 16V, 10%
0.36H Inductor, Inductance 20%, DCR 7% N-Channel Power MOSFET N-Channel Power MOSFET 562 100 2.87k 2.87k 499 147k Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1%
33
FN6890.2 April 29, 2010
ISL62882, ISL62882B
2-Phase CPU Application Reference Design Bill of Materials (Continued)
QTY 2 3 1 1 4 1 3 1 1 1 1 1 1 2 2 1 1 REFERENCE R17, R18 R19, R71, R72 R23 R26 R20, R40, R56, R57 R30 R37, R88, R90 R38 R4 R41 R42 R50 R6 R63, R65 R8, R9 R7 U6 VALUE 10 10k 1.91k 82.5 0 1k 1 11k DNP 2.61k Thick Film Chip Resistor, 1% GENERIC PANASONIC GENERIC GENERIC GENERIC H2511-02611-1/16W1 ERT-J1VR103J H2511-09311-1/16W1 H2511-08061-1/16W1 H2511-03651-1/16W1 SM0603 SM0603 SM0603 SM0603 SM0805 DESCRIPTION Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% MANUFACTURER GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC GENERIC PART NUMBER H2511-00100-1/16W1 H2511-01002-1/16W1 H2511-01911-1/16W1 H2511-082R5-1/16W1 H2511-00R00-1/16W1 H2511-01001-1/16W1 H2511-01R00-1/16W1 H2511-01102-1/16W1 PACKAGE SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603 SM0603
10k NTC Thermistor, 10k NTC 9.31k 8.06k 3.65k DNP 412k Thick Film Chip Resistor, 1% IMVP-6.5 PWM Controller Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1% Thick Film Chip Resistor, 1%
GENERIC INTERSIL
H2511-04123-1/16W1 ISL62882HRTZ
SM0603 QFN-40
34
FN6890.2 April 29, 2010
ISL62882, ISL62882B
Typical Performance
92 90 EFFICIENCY (%) 88 86 82 80 78 76 74 72 70 0 5 10 15 20 30 IOUT (A) 25 35 40 45 50 55 VIN = 19V VIN = 8V VIN = 12V VOUT (V) 84 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0 5 10 15 20 25 30 35 40 45 50 55 60 65 IOUT (A)
FIGURE 32. 2-PHASE CCM EFFICIENCY, VID = 1.075V, VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 33. 2-PHASE CCM LOAD LINE, VID = 1.075V, VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
90 85 EFFICIENCY (%) 80 75 70 65 60 55 0.1 1 10 100 VIN = 8V 0.885 0.875 VOUT (V) VIN = 12V VIN = 19V 0.865 0.855 0.845 0.835 0.825
0
1
2
3
4
5
6
IOUT (A)
7 8 9 10 11 12 13 14 15 IOUT (A)
FIGURE 34. 1-PHASE DEM EFFICIENCY, VID = 0.875V, DPRSLPVR IS ASSERTED FOR IOUT < 3A, VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V. SOLID LINES: ISL62882 EFFICIENCY, DOTTED LINES: WOULD-BE EFFICIENCY IF LGATE1b WAS NOT TURNED OFF IN DPRSLPVR MODE
FIGURE 35. 1-PHASE DEM LOAD LINE, VID = 0.875V, DPRSLPVR IS ASSERTED FOR IOUT < 3A VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 36. 2-PHASE CPU MODE SOFT-START, VIN = 19V, IO = 0A, VID = 0.95V, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2
FIGURE 37. 2-PHASE CPU MODESHUT DOWN, VIN = 19V, IO = 1A, VID = 0.95V, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2
35
FN6890.2 April 29, 2010
ISL62882, ISL62882B
Typical Performance (Continued)
FIGURE 38. 2-PHASE CPU MODE CLK_EN# DELAY, VIN = 19V, IO = 2A, VID = 1.5V, Ch1: PHASE1, Ch2: VO, Ch4: CLK_EN#
FIGURE 39. 2-PHASE CPU MODE PRE-CHARGED START UP, VIN = 19V, VID = 0.95V, Ch1: PHASE1, Ch2: VO, Ch4: VR_ON
FIGURE 40. STEADY STATE, VIN = 19V, IO = 0A, VID = 1.075V, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2
FIGURE 41. STEADY STATE, VIN = 19V, IO = 35A, VID = 1.075V, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2
FIGURE 42. LOAD TRANSIENT RESPONSE WITH OVERSHOOT REDUCTION FUNCTION DISABLED, VIN = 19V, VID = 1.075V, IO = 15A/50A, di/dt = "FASTEST"
FIGURE 43. LOAD TRANSIENT RESPONSE WITH OVERSHOOT REDUCTION FUNCTION DISABLED, VIN = 19V, VID = 1.075V, IO = 15A/50A, di/dt = "FASTEST"
36
FN6890.2 April 29, 2010
ISL62882, ISL62882B
Typical Performance (Continued)
FIGURE 44. LOAD TRANSIENT RESPONSE WITH OVERSHOOT REDUCTION FUNCTION DISABLED, VIN = 19V, VID = 1.075V, IO = 15A/50A, di/dt = "FASTEST"
FIGURE 45. LOAD TRANSIENT RESPONSE WITH OVERSHOOT REDUCTION FUNCTION DISABLED, VIN = 19V, VID = 1.075V, IO = 15A/50A, di/dt = "FASTEST"
FIGURE 46. 2-PHASE CPU MODE DEEPER SLEEP MODE ENTRY/EXIT, IO = 1.5A, HFM VID = 1.075V, LFM VID = 0.875V, DEEPER SLEEP VID = 0.875V, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2, CH4: DPRSLPVR
FIGURE 47. 2-PHASE CPU MODE VID ON THE FLY, 1.075V/0.875V, 2-PHASE CONFIGURATION, PSI# = 1, DPRSLPVR = 0, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2
FIGURE 48. PHASE ADDING (PSI# TOGGLE), IO = 15A, VID = 1.075V, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2, Ch4: N/A
FIGURE 49. PHASE DROPPING (PSI# TOGGLE), IO = 15A, VID = 1.075V, Ch1: PHASE1, Ch2: VO, Ch3: PHASE2, Ch4: N/A
37
FN6890.2 April 29, 2010
ISL62882, ISL62882B
Typical Performance (Continued)
Phase Margin
Gain
FIGURE 50. TRANSIENT RESPONSE WITH OVERSHOOT REDUCTION FUNCTION ENABLED, VIN = 19V, VID = 0.95V, IO = 12A/51A, di/dt = "FASTEST", Ch1: PHASE1, Ch2: VO, Ch3: N/A, Ch4: LGATE1
FIGURE 51. 2-PHASE CPU MODE REFERENCE DESIGN LOOP GAIN T2(s) MEASUREMENT RESULT
1000 900 IMON-VSSSENSE (mV) 800 700 Z(f) (m) 600 500 400 300 200 100 0 0 5 10 15 20 25 30 IOUT (A) 35 40 45 50 SPEC VIN = 12V VIN = 8V VIN = 19V
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1k PSI# = 0, DPRSLPVR = 0, 1-Phase DE 100k 10k FREQUENCY (Hz) 1M PSI# = 1, DPRSLPVR = 0, 2-Phase CCM
FIGURE 52. IMON, VID = 1.075
FIGURE 53. REFERENCE DESIGN FDIM RESULT
FIGURE 54. 1-PHASE GPU MODE SOFT-START, DPRSLPVR=0, VIN = 8V, IO = 0A, VID = 1.2375V, Ch1: PHASE1, Ch2: VO
FIGURE 55. 1-PHASE GPU MODE SHUT DOWN, VIN = 8V, IO = 1A, VID = 1.2375V, Ch1: PHASE1, Ch2: VO
38
FN6890.2 April 29, 2010
ISL62882, ISL62882B
Typical Performance (Continued)
FIGURE 56. 1-PHASE GPU MODE VID TRANSITION, DPRSLPVR=0, IO = 2A, VID = 1.2375V/1.0375V, Ch2: VO, Ch3: VID4
FIGURE 57. 1-PHASE GPU MODE VID TRANSITION, DPRSLPVR=1, IO = 2A, VID = 1.2375V/1.0375V, Ch2: VO, Ch3: VID4
39
FN6890.2 April 29, 2010
ISL62882, ISL62882B
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 12/3/09 11/4/09 REVISION FN6890.2 FN6890.2 CHANGE Removed ISL62882A device from data sheet. Converted to new Intersil template. On page 19, Modes of Operation section last paragraph Changed from "Rbias = 147kohm enables the overshoot reduction function and Rbias = 47kohm disables it" to "Rbias = 147kohm disables the overshoot reduction function and Rbias = 47kohm enables it". Applied Intersil Standards as follows: Ordering information with notes and links, Added bold verbiage to Electrical spec conditions for over-temp and bolded min and max value columns. Pin Descriptions placed in Table. 8/18/09 - See attached .doc file for changes. 7/10/09: Updated Figures 1, 2, 10, 11 and 27. Per Jia, "All the drawings have updated the way ISEN capacitors are connected. They used to be connected to from ISEN to GND, now they are connected from ISEN to Vo. It's an application patch that helps to avoid false IBAL fault during phase dropping due to an IC design error." Changed "GND" to "VSUM-" for pins 10 and 11 in table 5. Pin 10 now reads "A capacitor (C9) decouples it to VSUM-. Place it in general proximity of the controller." Pin 11 now reads "A capacitor (C10) decouples it to VSUM-. Place it in general proximity of the controller." ___________________________________ 5/19/09: Changed under Recommended Operating Conditions- Battery Voltage VIN from "+5V to 21V" to "+5V to 25V" Initial Release to web
8/24/09
FN6890.1
04/01/09
FN6890.0
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL62882, ISL62882B To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 40
FN6890.2 April 29, 2010
ISL62882, ISL62882B
Package Outline Drawing
L40.5x5
40 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 4/07
4X 3.60 5.00
A
B
36X 0.40
6
6 PIN 1 INDEX AREA
PIN #1 INDEX AREA
5.00
(4X)
0.15
TOP VIEW
40X 0.4 0 .
BOTTOM VIEW
0.20
b
0.10 M
3.50
C
AB
PACKAGE OUTLINE
0.40
0.750
SEE DETAIL Au // 0.10 C C BASE PLANE SEATING PLANE 0.08 C
SIDE VIEW
0.050
5.00
3.50
(36X 0 ..40) 0.2 REF
C
5
(40X 0.20)
0.00 MIN 0.05 MAX
(40X 0.60)
DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.0 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.27mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
41
FN6890.2 April 29, 2010
ISL62882, ISL62882B
Package Outline Drawing
L48.6x6
48 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 4/07
4X 4.4 6.00 A B 6 PIN 1 INDEX AREA 37 36 44X 0.40 48 1 6 PIN #1 INDEX AREA
6.00
4 .40 0.1
25 (4X) 0.15 24
TOP VIEW
12 13
0.10 M C A B 0.05 M C
48X 0.45 0.1
BOTTOM VIEW
4 48X 0.20
SEE DETAIL "X"
0.10 C BASE PLANE
MAX 0.80 ( 5. 75 TYP ) ( 44 X 0 . 40 )
SIDE VIEW
C
SEATING PLANE 0.08 C
(
4. 40 )
C ( 48X 0 . 20 )
0 . 2 REF
5
0 . 00 MIN. 0 . 05 MAX. ( 48X 0 . 65 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.0 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
42
FN6890.2 April 29, 2010

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